From: Andrew Jeffery <andrew@aj.id.au>
To: linux-mmc@vger.kernel.org
Cc: ulf.hansson@linaro.org, linux-aspeed@lists.ozlabs.org,
Andrew Jeffery <andrew@aj.id.au>,
openbmc@lists.ozlabs.org, ryanchen.aspeed@gmail.com,
adrian.hunter@intel.com, linux-kernel@vger.kernel.org,
joel@jms.id.au, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 0/2] mmc: sdhci-of-aspeed: Fixes for AST2600 eMMC support
Date: Fri, 30 Aug 2019 17:16:42 +0930 [thread overview]
Message-ID: <20190830074644.10936-1-andrew@aj.id.au> (raw)
Hello,
The ASPEED SDHCI driver patches sent previously were based on testing on the
AST2500. The SD controllers in the 2500 and 2600 had the same register layout
according to the documentation, so we added the necessary devicetree compatible
string at the same time.
Now that I've got access to 2600 hardware with an eMMC chip I have a couple of
patches that are fixes enabling support for it. I don't think the first patch
is too controversial - in some cases we weren't ensuring the clock was enabled
before returning from the set_clock() callback.
I'm a bit unsure about the second patch though which enables use of
max-frequency in the devicetree, it feels a bit hacky so I'm looking for any
suggestions on the approach.
Please review!
Andrew
Andrew Jeffery (2):
mmc: sdhci-of-aspeed: Uphold clocks-on post-condition of set_clock()
mmc: sdhci-of-aspeed: Allow max-frequency limitation of SDCLK
drivers/mmc/host/sdhci-of-aspeed.c | 21 +++++++++++++++++----
1 file changed, 17 insertions(+), 4 deletions(-)
--
2.20.1
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next reply other threads:[~2019-08-30 7:46 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-30 7:46 Andrew Jeffery [this message]
2019-08-30 7:46 ` [PATCH 1/2] mmc: sdhci-of-aspeed: Uphold clocks-on post-condition of set_clock() Andrew Jeffery
2019-08-30 8:01 ` Ulf Hansson
2019-08-30 8:07 ` Andrew Jeffery
2019-08-30 8:29 ` Ulf Hansson
2019-08-30 7:46 ` [PATCH 2/2] mmc: sdhci-of-aspeed: Allow max-frequency limitation of SDCLK Andrew Jeffery
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