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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id r23sm554511pjo.22.2019.09.03.15.22.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 03 Sep 2019 15:22:17 -0700 (PDT) Date: Tue, 3 Sep 2019 16:22:15 -0600 From: Mathieu Poirier To: Leo Yan Subject: Re: [PATCH v1 1/3] perf cs-etm: Refactor instruction size handling Message-ID: <20190903222215.GD25787@xps15> References: <20190830062421.31275-1-leo.yan@linaro.org> <20190830062421.31275-2-leo.yan@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190830062421.31275-2-leo.yan@linaro.org> User-Agent: Mutt/1.9.4 (2018-02-28) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190903_152219_770378_E0537318 X-CRM114-Status: GOOD ( 22.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Suzuki K Poulose , Alexander Shishkin , linux-kernel@vger.kernel.org, Arnaldo Carvalho de Melo , Adrian Hunter , Namhyung Kim , Robert Walker , Jiri Olsa , linux-arm-kernel@lists.infradead.org, Mike Leach Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Aug 30, 2019 at 02:24:19PM +0800, Leo Yan wrote: > There has several code pieces need to know the instruction size, but > now every place calculates the instruction size separately. > > This patch refactors to create a new function cs_etm__instr_size() as > a central place to analyze the instruction length based on ISA type > and instruction value. > > Signed-off-by: Leo Yan > --- > tools/perf/util/cs-etm.c | 44 +++++++++++++++++++++++++++------------- > 1 file changed, 30 insertions(+), 14 deletions(-) > > diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c > index b3a5daaf1a8f..882a0718033d 100644 > --- a/tools/perf/util/cs-etm.c > +++ b/tools/perf/util/cs-etm.c > @@ -914,6 +914,26 @@ static inline int cs_etm__t32_instr_size(struct cs_etm_queue *etmq, > return ((instrBytes[1] & 0xF8) >= 0xE8) ? 4 : 2; > } > > +static inline int cs_etm__instr_size(struct cs_etm_queue *etmq, > + u8 trace_chan_id, > + enum cs_etm_isa isa, > + u64 addr) > +{ > + int insn_len; > + > + /* > + * T32 instruction size might be 32-bit or 16-bit, decide by calling > + * cs_etm__t32_instr_size(). > + */ > + if (isa == CS_ETM_ISA_T32) > + insn_len = cs_etm__t32_instr_size(etmq, trace_chan_id, addr); > + /* Otherwise, A64 and A32 instruction size are always 32-bit. */ > + else > + insn_len = 4; > + > + return insn_len; > +} > + > static inline u64 cs_etm__first_executed_instr(struct cs_etm_packet *packet) > { > /* Returns 0 for the CS_ETM_DISCONTINUITY packet */ > @@ -938,19 +958,23 @@ static inline u64 cs_etm__instr_addr(struct cs_etm_queue *etmq, > const struct cs_etm_packet *packet, > u64 offset) > { > + int insn_len; > + > if (packet->isa == CS_ETM_ISA_T32) { > u64 addr = packet->start_addr; > > while (offset > 0) { > - addr += cs_etm__t32_instr_size(etmq, > - trace_chan_id, addr); > + addr += cs_etm__instr_size(etmq, trace_chan_id, > + packet->isa, addr); > offset--; > } > return addr; > } > > - /* Assume a 4 byte instruction size (A32/A64) */ > - return packet->start_addr + offset * 4; > + /* Return instruction size for A32/A64 */ > + insn_len = cs_etm__instr_size(etmq, trace_chan_id, > + packet->isa, packet->start_addr); > + return packet->start_addr + offset * insn_len; This patch will work but from where I stand it makes things difficult to understand more than anything else. It is also adding coupling between function cs_etm__instr_addr() and cs_etm__instr_size(), meaning the code needs to be carefully inspected in order to make changes to either one. Last but not least function cs_etm__instr_size() isn't used in the upcoming patches. I really don't see what is gained here. Thanks, Mathieu > } > > static void cs_etm__update_last_branch_rb(struct cs_etm_queue *etmq, > @@ -1090,16 +1114,8 @@ static void cs_etm__copy_insn(struct cs_etm_queue *etmq, > return; > } > > - /* > - * T32 instruction size might be 32-bit or 16-bit, decide by calling > - * cs_etm__t32_instr_size(). > - */ > - if (packet->isa == CS_ETM_ISA_T32) > - sample->insn_len = cs_etm__t32_instr_size(etmq, trace_chan_id, > - sample->ip); > - /* Otherwise, A64 and A32 instruction size are always 32-bit. */ > - else > - sample->insn_len = 4; > + sample->insn_len = cs_etm__instr_size(etmq, trace_chan_id, > + packet->isa, sample->ip); > > cs_etm__mem_access(etmq, trace_chan_id, sample->ip, > sample->insn_len, (void *)sample->insn); > -- > 2.17.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel