From: Shawn Guo <shawnguo@kernel.org>
To: Fancy Fang <chen.fang@nxp.com>
Cc: Aisheng Dong <aisheng.dong@nxp.com>,
Abel Vesa <abel.vesa@nxp.com>, Anson Huang <anson.huang@nxp.com>,
"sboyd@kernel.org" <sboyd@kernel.org>,
"mturquette@baylibre.com" <mturquette@baylibre.com>,
Jana Build <jana.build@nxp.com>,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
LnxRevLi <LnxRevLi@nxp.com>, dl-linux-imx <linux-imx@nxp.com>,
"kernel@pengutronix.de" <kernel@pengutronix.de>,
"festevam@gmail.com" <festevam@gmail.com>,
"s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 2/2] clk: imx7ulp: remove IMX7ULP_CLK_MIPI_PLL clock
Date: Wed, 11 Sep 2019 14:45:58 +0800 [thread overview]
Message-ID: <20190911064556.GD17142@dragon> (raw)
In-Reply-To: <20190823003600.8317-2-chen.fang@nxp.com>
On Fri, Aug 23, 2019 at 12:37:35AM +0000, Fancy Fang wrote:
> The mipi pll clock comes from the MIPI PHY PLL output, so
> it should not be a fixed clock.
>
> MIPI PHY PLL is in the MIPI DSI space, and it is used as
> the bit clock for transferring the pixel data out and its
> output clock is configured according to the display mode.
>
> So it should be used only for MIPI DSI and not be exported
> out for other usages.
>
> Signed-off-by: Fancy Fang <chen.fang@nxp.com>
> ---
> .../devicetree/bindings/clock/imx7ulp-clock.txt | 1 -
> drivers/clk/imx/clk-imx7ulp.c | 3 +--
> include/dt-bindings/clock/imx7ulp-clock.h | 15 +++++++--------
> 3 files changed, 8 insertions(+), 11 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
> index a4f8cd478f92..93d89adb7afe 100644
> --- a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
> @@ -82,7 +82,6 @@ pcc2: pcc2@403f0000 {
> <&scg1 IMX7ULP_CLK_APLL_PFD0>,
> <&scg1 IMX7ULP_CLK_UPLL>,
> <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
> - <&scg1 IMX7ULP_CLK_MIPI_PLL>,
> <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
> <&scg1 IMX7ULP_CLK_ROSC>,
> <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
> diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c
> index 2022d9bead91..459b120b71d5 100644
> --- a/drivers/clk/imx/clk-imx7ulp.c
> +++ b/drivers/clk/imx/clk-imx7ulp.c
> @@ -28,7 +28,7 @@ static const char * const scs_sels[] = { "dummy", "sosc", "sirc", "firc", "dumm
> static const char * const ddr_sels[] = { "apll_pfd_sel", "upll", };
> static const char * const nic_sels[] = { "firc", "ddr_clk", };
> static const char * const periph_plat_sels[] = { "dummy", "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", };
> -static const char * const periph_bus_sels[] = { "dummy", "sosc_bus_clk", "mpll", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };
> +static const char * const periph_bus_sels[] = { "dummy", "sosc_bus_clk", "dummy", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };
> static const char * const arm_sels[] = { "divcore", "dummy", "dummy", "hsrun_divcore", };
>
> /* used by sosc/sirc/firc/ddr/spll/apll dividers */
> @@ -75,7 +75,6 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np)
> clks[IMX7ULP_CLK_SOSC] = imx_obtain_fixed_clk_hw(np, "sosc");
> clks[IMX7ULP_CLK_SIRC] = imx_obtain_fixed_clk_hw(np, "sirc");
> clks[IMX7ULP_CLK_FIRC] = imx_obtain_fixed_clk_hw(np, "firc");
> - clks[IMX7ULP_CLK_MIPI_PLL] = imx_obtain_fixed_clk_hw(np, "mpll");
> clks[IMX7ULP_CLK_UPLL] = imx_obtain_fixed_clk_hw(np, "upll");
>
> /* SCG1 */
> diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h
> index 6f66f9005c81..f8d34fb4378f 100644
> --- a/include/dt-bindings/clock/imx7ulp-clock.h
> +++ b/include/dt-bindings/clock/imx7ulp-clock.h
> @@ -49,15 +49,14 @@
> #define IMX7ULP_CLK_NIC1_DIV 36
> #define IMX7ULP_CLK_NIC1_BUS_DIV 37
> #define IMX7ULP_CLK_NIC1_EXT_DIV 38
> -#define IMX7ULP_CLK_MIPI_PLL 39
> -#define IMX7ULP_CLK_SIRC 40
> -#define IMX7ULP_CLK_SOSC_BUS_CLK 41
> -#define IMX7ULP_CLK_FIRC_BUS_CLK 42
> -#define IMX7ULP_CLK_SPLL_BUS_CLK 43
> -#define IMX7ULP_CLK_HSRUN_SYS_SEL 44
> -#define IMX7ULP_CLK_HSRUN_CORE_DIV 45
> +#define IMX7ULP_CLK_SIRC 39
> +#define IMX7ULP_CLK_SOSC_BUS_CLK 40
> +#define IMX7ULP_CLK_FIRC_BUS_CLK 41
> +#define IMX7ULP_CLK_SPLL_BUS_CLK 42
> +#define IMX7ULP_CLK_HSRUN_SYS_SEL 43
> +#define IMX7ULP_CLK_HSRUN_CORE_DIV 44
No. These clock IDs need to be stable, as they are referred by DT.
If you want to remove an ID, just remove it, keep others unchanged.
Shawn
>
> -#define IMX7ULP_CLK_SCG1_END 46
> +#define IMX7ULP_CLK_SCG1_END 45
>
> /* PCC2 */
> #define IMX7ULP_CLK_DMA1 0
> --
> 2.17.1
>
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next prev parent reply other threads:[~2019-09-11 6:46 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-23 0:37 [PATCH 1/2] ARM: dts: imx7ulp: remove mipi pll clock node Fancy Fang
2019-08-23 0:37 ` [PATCH 2/2] clk: imx7ulp: remove IMX7ULP_CLK_MIPI_PLL clock Fancy Fang
2019-09-11 6:45 ` Shawn Guo [this message]
2019-09-11 6:42 ` [PATCH 1/2] ARM: dts: imx7ulp: remove mipi pll clock node Shawn Guo
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