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spf=fail smtp.mailfrom=ckeepax@opensource.cirrus.com Received: from ediex01.ad.cirrus.com ([87.246.76.36]) by mx0b-001ae601.pphosted.com with ESMTP id 2v37m197ex-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Wed, 18 Sep 2019 09:31:59 -0500 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1591.10; Wed, 18 Sep 2019 15:31:57 +0100 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.1591.10 via Frontend Transport; Wed, 18 Sep 2019 15:31:57 +0100 Received: from ediswmail.ad.cirrus.com (ediswmail.ad.cirrus.com [198.61.86.93]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id DA4CD2C3; Wed, 18 Sep 2019 14:31:57 +0000 (UTC) Date: Wed, 18 Sep 2019 14:31:57 +0000 From: Charles Keepax To: Sylwester Nawrocki Subject: Re: [PATCH v1 4/9] ASoC: wm8994: Add support for MCLKn clock gating Message-ID: <20190918143157.GH10204@ediswmail.ad.cirrus.com> References: <20190918104634.15216-1-s.nawrocki@samsung.com> <20190918104634.15216-5-s.nawrocki@samsung.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190918104634.15216-5-s.nawrocki@samsung.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-Proofpoint-SPF-Result: fail X-Proofpoint-SPF-Record: v=spf1 include:spf-001ae601.pphosted.com include:spf.protection.outlook.com -all X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 bulkscore=0 phishscore=0 priorityscore=1501 spamscore=0 adultscore=0 suspectscore=0 mlxscore=0 mlxlogscore=999 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1908290000 definitions=main-1909180144 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190918_073208_556522_BFBE14FB X-CRM114-Status: GOOD ( 20.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, linux-samsung-soc@vger.kernel.org, b.zolnierkie@samsung.com, sbkim73@samsung.com, patches@opensource.cirrus.com, broonie@kernel.org, lgirdwood@gmail.com, krzk@kernel.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, m.szyprowski@samsung.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Sep 18, 2019 at 12:46:29PM +0200, Sylwester Nawrocki wrote: > As an intermediate step before covering the clocking subsystem > of the CODEC entirely by the clk API add handling of external CODEC's > master clocks in DAPM events when the AIFn clocks are sourced directly > from MCLKn; when FLLn are used we enable/disable respective MCLKn > before/after FLLn is enabled/disabled. > > Signed-off-by: Sylwester Nawrocki > --- > @@ -2260,8 +2321,28 @@ static int _wm8994_set_fll(struct snd_soc_component *component, int id, int src, > /* Clear any pending completion from a previous failure */ > try_wait_for_completion(&wm8994->fll_locked[id]); > > + switch (src) { > + case WM8994_FLL_SRC_MCLK1: > + mclk = control->mclk[0].clk; > + break; > + case WM8994_FLL_SRC_MCLK2: > + mclk = control->mclk[1].clk; > + break; > + default: > + mclk = NULL; > + } > + > /* Enable (with fractional mode if required) */ > if (freq_out) { > + if (mclk) { > + ret = clk_prepare_enable(mclk); > + if (ret < 0) { > + dev_err(component->dev, > + "Failed to enable MCLK for FLL%d\n", > + id + 1); > + return ret; > + } > + } > /* Enable VMID if we need it */ > if (!was_enabled) { > active_reference(component); > @@ -2315,6 +2396,8 @@ static int _wm8994_set_fll(struct snd_soc_component *component, int id, int src, > > active_dereference(component); > } > + if (mclk) > + clk_disable_unprepare(mclk); I don't think this works in the case of changing active FLLs. The driver looks like it allows changing the FLL configuration whilst the FLL is already active in which case it you would have two wm8994_set_fll calls enabling the FLL but only a single one disabling it. Resulting in the FLL being off but the MCLK being left enabled. Thanks, Charles _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel