From: James Morse <james.morse@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>
Subject: [PATCH 2/4] arm64: Fake the IminLine size on systems affected by Neoverse-N1 #1542419
Date: Wed, 2 Oct 2019 10:49:33 +0100 [thread overview]
Message-ID: <20191002094935.48848-3-james.morse@arm.com> (raw)
In-Reply-To: <20191002094935.48848-1-james.morse@arm.com>
Systems affected by Neoverse-N1 #1542419 support DIC so do not need to
perform icache maintenance once new instructions are cleaned to the PoU.
For the errata workaround, the kernel hides DIC from user-space, so that
the unnecessary cache maintenance can be trapped by firmware.
To reduce the number of traps, produce a fake IminLine value based on
PAGE_SIZE.
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/cache.h | 3 ++-
arch/arm64/kernel/traps.c | 6 +++++-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
index 43da6dd29592..806e9dc2a852 100644
--- a/arch/arm64/include/asm/cache.h
+++ b/arch/arm64/include/asm/cache.h
@@ -11,6 +11,7 @@
#define CTR_L1IP_MASK 3
#define CTR_DMINLINE_SHIFT 16
#define CTR_IMINLINE_SHIFT 0
+#define CTR_IMINLINE_MASK 0xf
#define CTR_ERG_SHIFT 20
#define CTR_CWG_SHIFT 24
#define CTR_CWG_MASK 15
@@ -18,7 +19,7 @@
#define CTR_DIC_SHIFT 29
#define CTR_CACHE_MINLINE_MASK \
- (0xf << CTR_DMINLINE_SHIFT | 0xf << CTR_IMINLINE_SHIFT)
+ (0xf << CTR_DMINLINE_SHIFT | CTR_IMINLINE_MASK << CTR_IMINLINE_SHIFT)
#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
index 465f0a0f8f0a..991647a65fe8 100644
--- a/arch/arm64/kernel/traps.c
+++ b/arch/arm64/kernel/traps.c
@@ -470,9 +470,13 @@ static void ctr_read_handler(unsigned int esr, struct pt_regs *regs)
int rt = ESR_ELx_SYS64_ISS_RT(esr);
unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0);
- if (cpus_have_const_cap(ARM64_WORKAROUND_1542419))
+ if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) {
val &= ~BIT(CTR_DIC_SHIFT);
+ val &= ~CTR_IMINLINE_MASK;
+ val |= PAGE_SHIFT - 2;
+ }
+
pt_regs_write_reg(regs, rt, val);
arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
--
2.20.1
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next prev parent reply other threads:[~2019-10-02 9:50 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-02 9:49 [PATCH 0/4] arm64: errata: Workaround Neoverse-N1 #1542419 James Morse
2019-10-02 9:49 ` [PATCH 1/4] arm64: errata: Hide CTR_EL0.DIC on systems affected by " James Morse
2019-10-07 9:38 ` Suzuki K Poulose
2019-10-11 18:22 ` James Morse
2019-10-02 9:49 ` James Morse [this message]
2019-10-07 9:48 ` [PATCH 2/4] arm64: Fake the IminLine size " Suzuki K Poulose
2019-10-11 18:22 ` James Morse
2019-10-02 9:49 ` [PATCH 3/4] arm64: compat: Workaround Neoverse-N1 #1542419 for compat user-space James Morse
2019-10-02 9:49 ` [PATCH 4/4] arm64: ftrace: Ensure synchronisation in PLT setup for Neoverse-N1 #1542419 James Morse
2019-10-04 10:33 ` Will Deacon
2019-10-04 14:21 ` James Morse
2019-10-04 10:31 ` [PATCH 0/4] arm64: errata: Workaround " Will Deacon
2019-10-04 14:19 ` James Morse
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