From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65418C4360C for ; Tue, 8 Oct 2019 19:47:29 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 39C5421835 for ; Tue, 8 Oct 2019 19:47:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="QPrO2es0" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 39C5421835 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=breakpoint.cc Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xgOS+R1Co7wK07LXToFattjDtBsbOKwtyHZNvk0am/E=; b=QPrO2es0n4psuo siRjoTPdmNpuSgb247ztOCOb7KMSBxoYz0YwfPYIqQ5l4rLHZnYOL0+/e/BFu90JWIB3FbcT8GLyB 7YrbsHnWIuso828mKmAJMlIHGTaCQRMn4sRv3cgS/dBnHce9FsiIy3kB2GX3z/nG3ivE59+jqJwSg J8MG6/7VxaVyx0w4AtNyMFcgIA/Lbab8ac1I/lEsppn1QVTR5/kscyMpkcnr4nCyOdi0d9wEzWScR UZkNI+xc4xdF2y4yKgmVJX7vrDXXQE7cnYWMSxPiWFDy0p/V5ay84+mmFBCFoXPGmDOYgyWniyIzs CKyASTA0/71BJKac1eqw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iHvSC-00007e-SP; Tue, 08 Oct 2019 19:47:28 +0000 Received: from chamillionaire.breakpoint.cc ([2a0a:51c0:0:12e:520::1]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iHvSA-00006t-HF for linux-arm-kernel@lists.infradead.org; Tue, 08 Oct 2019 19:47:27 +0000 Received: from bigeasy by Chamillionaire.breakpoint.cc with local (Exim 4.92) (envelope-from ) id 1iHvS9-0005uF-6K; Tue, 08 Oct 2019 21:47:25 +0200 Date: Tue, 8 Oct 2019 21:47:25 +0200 From: Sebastian Andrzej Siewior To: Arnd Bergmann Subject: Re: [RFC PATCH 0/3] Queued spinlocks/RW-locks for ARM Message-ID: <20191008194724.evlk3bnomcz3kxwg@flow> References: <20191007214439.27891-1-sebastian@breakpoint.cc> <56004687-af3e-3b8b-c9b5-21cd653db12b@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20180716 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191008_124726_570576_7DB478A2 X-CRM114-Status: GOOD ( 11.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Zijlstra , Russell King , Ingo Molnar , Waiman Long , Will Deacon , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2019-10-08 16:32:27 [+0200], Arnd Bergmann wrote: > On Tue, Oct 8, 2019 at 3:36 PM Waiman Long wrote: > > In x86, the lock instruction prefix is patched out when running on UP > > system. This downgrades the atomic cmpxchg to non-atomic one. We may do > > something similar in other architectures. > > Unfortunately, the atomic macros cannot trivially be made cheaper > on non-SMP systems based on load-locked/store-conditional > based architectures, as there may be an interrupt in-between, > and disabling interrupts would likely be more expensive. > > However, there might be a way to take a shortcut out of > queued_spin_lock() using asm-goto combined with the ARM > __ALT_SMP_ASM() macro. The smp_xchg16_relaxed() snippet above looked good. I would buy it :) Where are you heading with __ALT_SMP_ASM()? > Arnd Sebastian _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel