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Received: from j217100.upc-j.chello.nl ([24.132.217.100] helo=noisy.programming.kicks-ass.net) by merlin.infradead.org with esmtpsa (Exim 4.92.2 #3 (Red Hat Linux)) id 1iI7br-0000Dd-2K; Wed, 09 Oct 2019 08:46:15 +0000 Received: from hirez.programming.kicks-ass.net (hirez.programming.kicks-ass.net [192.168.1.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by noisy.programming.kicks-ass.net (Postfix) with ESMTPS id 6A82730034F; Wed, 9 Oct 2019 10:45:18 +0200 (CEST) Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id 1D79E20BCA6A9; Wed, 9 Oct 2019 10:46:10 +0200 (CEST) Date: Wed, 9 Oct 2019 10:46:10 +0200 From: Peter Zijlstra To: Arnd Bergmann Subject: Re: [RFC PATCH 0/3] Queued spinlocks/RW-locks for ARM Message-ID: <20191009084610.GG2311@hirez.programming.kicks-ass.net> References: <20191007214439.27891-1-sebastian@breakpoint.cc> <56004687-af3e-3b8b-c9b5-21cd653db12b@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Russell King , Sebastian Andrzej Siewior , Ingo Molnar , Waiman Long , Will Deacon , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Oct 08, 2019 at 04:32:27PM +0200, Arnd Bergmann wrote: > diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h > index 8b701f8e175c..6bf4964c105c 100644 > --- a/arch/arm/include/asm/cmpxchg.h > +++ b/arch/arm/include/asm/cmpxchg.h > @@ -114,6 +114,24 @@ static inline unsigned long __xchg(unsigned long > x, volatile void *ptr, int size > return ret; > } > > +#ifdef CONFIG_CPU_V6 > +static inline unsigned short smp_xchg16_relaxed(volatile unsigned > short *ptr, unsigned short x) > +{ > + unsigned short ret, tmp; > + asm volatile("@ smp_xchg16_relaxed\n" > + ".arch armv6k\n" > + "1: ldrexh %0, [%3]\n" > + " strexh %1, %2, [%3]\n" > + " teq %1, #0\n" > + " bne 1b" > + : "=&r" (ret), "=&r" (tmp) > + : "r" (x), "r" (ptr) > + : "memory", "cc"); > + return ret; > +} > +#define smp_xchg16_relaxed smp_xchg16_relaxed > +#endif Why is this not in __xchg() as a variant for case 2 ? _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel