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Received: from j217100.upc-j.chello.nl ([24.132.217.100] helo=noisy.programming.kicks-ass.net) by merlin.infradead.org with esmtpsa (Exim 4.92.2 #3 (Red Hat Linux)) id 1iI9eG-0001UI-E0; Wed, 09 Oct 2019 10:56:52 +0000 Received: from hirez.programming.kicks-ass.net (hirez.programming.kicks-ass.net [192.168.1.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by noisy.programming.kicks-ass.net (Postfix) with ESMTPS id 5B7D33062B5; Wed, 9 Oct 2019 12:55:58 +0200 (CEST) Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id 24C4320247620; Wed, 9 Oct 2019 12:56:50 +0200 (CEST) Date: Wed, 9 Oct 2019 12:56:50 +0200 From: Peter Zijlstra To: Arnd Bergmann Subject: Re: [RFC PATCH 0/3] Queued spinlocks/RW-locks for ARM Message-ID: <20191009105650.GM2328@hirez.programming.kicks-ass.net> References: <20191007214439.27891-1-sebastian@breakpoint.cc> <56004687-af3e-3b8b-c9b5-21cd653db12b@redhat.com> <20191009084610.GG2311@hirez.programming.kicks-ass.net> <20191009093118.GJ2328@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Russell King , Sebastian Andrzej Siewior , Ingo Molnar , Waiman Long , Will Deacon , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Oct 09, 2019 at 12:31:24PM +0200, Arnd Bergmann wrote: > On Wed, Oct 9, 2019 at 11:31 AM Peter Zijlstra wrote: > > On Wed, Oct 09, 2019 at 10:57:25AM +0200, Arnd Bergmann wrote: > > > On Wed, Oct 9, 2019 at 10:46 AM Peter Zijlstra wrote: > > > > Why is this not in __xchg() as a variant for case 2 ? > > > > > > ldrexh/strexh are instructions that are only available on SMP-capable > > > architecture revisions (ARMv6K or higher). When building a kernel > > > that runs both on pre-K ARMv6 uniprocessor systems and on later > > > SMP systems, __xchg() can only do 32-bit ldrex/strex. > > > > You can do u16 xchg using a u32 ll/sc, see openrisc's xchg_small(). > > Ah, right. That would be much nicer than my smp_xchg16_relaxed() > hack to get the corner case working, as it avoids the ugly special > case in qspinlock.h. > > Would this still have comparable performance characteristics? I suppose so.. > I assume the 16-bit xchg_relaxed() in qspinlock.c was meant as > an optimization for x86 and other cmpxchg based architectures but > doesn't actually help on ll/sc based architectures that get the > reservation on the whole cache line anyway? It does actually help here too, because it allows other operations to be regular load/stores. Look at the #if _Q_PENDING_BITS==8 in qspinlock.c, as opposed to the #else where they're all atomic_*(). _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel