From: Mike Leach <mike.leach@linaro.org>
To: mike.leach@linaro.org, coresight@lists.linaro.org,
linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org
Cc: gregkh@linuxfoundation.org, suzuki.poulose@arm.com,
mathieu.poirier@linaro.org, corbet@lwn.net
Subject: [PATCH v3 04/11] coresight: etm4x: Fix issues with start-stop logic.
Date: Tue, 15 Oct 2019 22:19:57 +0100 [thread overview]
Message-ID: <20191015212004.24748-5-mike.leach@linaro.org> (raw)
In-Reply-To: <20191015212004.24748-1-mike.leach@linaro.org>
Fixes the following issues when using the ETMv4 start-stop logic.
1) Setting a start or a stop address should not automatically set the
start-stop status to 'on'. The value set by the user in 'mode' must
be respected or start instances could be missed.
2) Missing API for controlling TRCVIPCSSCTLR - start stop control by
PE comparators.
3) Default ETM configuration sets a trace all range, and correctly sets
the start-stop status bit. This was not being correctly reflected in
the 'mode' parameter.
Signed-off-by: Mike Leach <mike.leach@linaro.org>
---
.../coresight/coresight-etm4x-sysfs.c | 39 +++++++++++++++++--
drivers/hwtracing/coresight/coresight-etm4x.c | 1 +
2 files changed, 36 insertions(+), 4 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index 45fa7743eea4..2dbad7162557 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -217,6 +217,7 @@ static ssize_t reset_store(struct device *dev,
/* No start-stop filtering for ViewInst */
config->vissctlr = 0x0;
+ config->vipcssctlr = 0x0;
/* Disable seq events */
for (i = 0; i < drvdata->nrseqstate-1; i++)
@@ -1059,8 +1060,6 @@ static ssize_t addr_start_store(struct device *dev,
config->addr_val[idx] = (u64)val;
config->addr_type[idx] = ETM_ADDR_TYPE_START;
config->vissctlr |= BIT(idx);
- /* SSSTATUS, bit[9] - turn on start/stop logic */
- config->vinst_ctrl |= BIT(9);
spin_unlock(&drvdata->spinlock);
return size;
}
@@ -1116,8 +1115,6 @@ static ssize_t addr_stop_store(struct device *dev,
config->addr_val[idx] = (u64)val;
config->addr_type[idx] = ETM_ADDR_TYPE_STOP;
config->vissctlr |= BIT(idx + 16);
- /* SSSTATUS, bit[9] - turn on start/stop logic */
- config->vinst_ctrl |= BIT(9);
spin_unlock(&drvdata->spinlock);
return size;
}
@@ -1274,6 +1271,39 @@ static ssize_t addr_exlevel_s_ns_store(struct device *dev,
}
static DEVICE_ATTR_RW(addr_exlevel_s_ns);
+static ssize_t vinst_pe_cmp_start_stop_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ unsigned long val;
+ struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ struct etmv4_config *config = &drvdata->config;
+
+ if (!drvdata->nr_pe_cmp)
+ return -EINVAL;
+ val = config->vipcssctlr;
+ return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
+}
+static ssize_t vinst_pe_cmp_start_stop_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ unsigned long val;
+ struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ struct etmv4_config *config = &drvdata->config;
+
+ if (kstrtoul(buf, 16, &val))
+ return -EINVAL;
+ if (!drvdata->nr_pe_cmp)
+ return -EINVAL;
+
+ spin_lock(&drvdata->spinlock);
+ config->vipcssctlr = val;
+ spin_unlock(&drvdata->spinlock);
+ return size;
+}
+static DEVICE_ATTR_RW(vinst_pe_cmp_start_stop);
+
static ssize_t seq_idx_show(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -2080,6 +2110,7 @@ static struct attribute *coresight_etmv4_attrs[] = {
&dev_attr_addr_ctxtype.attr,
&dev_attr_addr_context.attr,
&dev_attr_addr_exlevel_s_ns.attr,
+ &dev_attr_vinst_pe_cmp_start_stop.attr,
&dev_attr_seq_idx.attr,
&dev_attr_seq_state.attr,
&dev_attr_seq_event.attr,
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index efe120925f9d..d5148afdbe80 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -887,6 +887,7 @@ static void etm4_set_default_filter(struct etmv4_config *config)
* in the started state
*/
config->vinst_ctrl |= BIT(9);
+ config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
/* No start-stop filtering for ViewInst */
config->vissctlr = 0x0;
--
2.17.1
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next prev parent reply other threads:[~2019-10-15 21:21 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-15 21:19 [PATCH v3 00/11] coresight: etm4x: Fixes and updates for sysfs API Mike Leach
2019-10-15 21:19 ` [PATCH v3 01/11] coresight: etm4x: Fixes for ETM v4.4 architecture updates Mike Leach
2019-10-17 17:55 ` Mathieu Poirier
2019-10-15 21:19 ` [PATCH v3 02/11] coresight: etm4x: Fix input validation for sysfs Mike Leach
2019-10-17 17:56 ` Mathieu Poirier
2019-10-15 21:19 ` [PATCH v3 03/11] coresight: etm4x: Add missing API to set EL match on address filters Mike Leach
2019-10-17 18:00 ` Mathieu Poirier
2019-10-17 19:25 ` Mathieu Poirier
2019-10-15 21:19 ` Mike Leach [this message]
2019-10-15 21:19 ` [PATCH v3 05/11] coresight: etm4x: Improve usability of sysfs - include/exclude addr Mike Leach
2019-10-15 21:19 ` [PATCH v3 06/11] coresight: etm4x: Improve usability of sysfs - CID and VMID masks Mike Leach
2019-10-15 21:20 ` [PATCH v3 07/11] coresight: etm4x: Add view comparator settings API to sysfs Mike Leach
2019-10-15 21:20 ` [PATCH v3 08/11] coresight: etm4x: Add missing single-shot control " Mike Leach
2019-10-17 20:17 ` Mathieu Poirier
2019-10-15 21:20 ` [PATCH v3 09/11] coresight: etm4x: docs: Update ABI doc for sysfs features added Mike Leach
2019-10-18 16:16 ` Mathieu Poirier
2019-10-15 21:20 ` [PATCH v3 10/11] coresight: docs: Create common sub-directory for coresight trace Mike Leach
2019-10-18 16:20 ` Mathieu Poirier
2019-10-18 17:31 ` Mathieu Poirier
2019-10-24 10:46 ` Mike Leach
2019-10-15 21:20 ` [PATCH v3 11/11] coresight: etm4x: docs: Adds detailed document for programming etm4x Mike Leach
2019-10-18 17:27 ` Mathieu Poirier
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