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* [PATCH] clk: imx8m: Use SYS_PLL1_800M as intermediate parent of CLK_ARM
@ 2019-10-22 19:21 Leonard Crestez
  2019-10-28  8:35 ` Shawn Guo
  2019-10-28  9:45 ` Stephen Boyd
  0 siblings, 2 replies; 3+ messages in thread
From: Leonard Crestez @ 2019-10-22 19:21 UTC (permalink / raw)
  To: Stephen Boyd, Shawn Guo
  Cc: Dong Aisheng, Jacky Bai, Anson Huang, Michael Turquette,
	linux-imx, kernel, Fabio Estevam, linux-clk, linux-arm-kernel,
	Abel Vesa

During cpu frequency switching the main "CLK_ARM" is reparented to an
intermediate "step" clock. On imx8mm and imx8mn the 24M oscillator is
used for this purpose but it is extremely slow, increasing wakeup
latencies to the point that i2c transactions can timeout and system
becomes unresponsive.

Fix by switching the "step" clk to SYS_PLL1_800M, matching the behavior
of imx8m cpufreq drivers in imx vendor tree.

This bug was not immediately apparent because upstream arm64 defconfig
uses the "performance" governor by default so no cpufreq transitions
happen.

Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm")
Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver")

Cc: stable@vger.kernel.org
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
---
 drivers/clk/imx/clk-imx8mm.c | 2 +-
 drivers/clk/imx/clk-imx8mn.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

This is marked as "cc: stable" because it has a large impact on common
usecases and it's difficult to debug.

This was sent with a different email workaround so hope it arrives OK.

diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index bbd212eb904e..a92942ea2045 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -588,11 +588,11 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
 
 	clks[IMX8MM_CLK_ARM] = imx_clk_cpu("arm", "arm_a53_div",
 					   clks[IMX8MM_CLK_A53_DIV],
 					   clks[IMX8MM_CLK_A53_SRC],
 					   clks[IMX8MM_ARM_PLL_OUT],
-					   clks[IMX8MM_CLK_24M]);
+					   clks[IMX8MM_SYS_PLL1_800M]);
 
 	imx_check_clocks(clks, ARRAY_SIZE(clks));
 
 	clk_data.clks = clks;
 	clk_data.clk_num = ARRAY_SIZE(clks);
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index ad7f2e527c70..3cd38eba58df 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -544,11 +544,11 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
 
 	clks[IMX8MN_CLK_ARM] = imx_clk_cpu("arm", "arm_a53_div",
 					   clks[IMX8MN_CLK_A53_DIV],
 					   clks[IMX8MN_CLK_A53_SRC],
 					   clks[IMX8MN_ARM_PLL_OUT],
-					   clks[IMX8MN_CLK_24M]);
+					   clks[IMX8MN_SYS_PLL1_800M]);
 
 	imx_check_clocks(clks, ARRAY_SIZE(clks));
 
 	clk_data.clks = clks;
 	clk_data.clk_num = ARRAY_SIZE(clks);
-- 
2.17.1


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2019-10-22 19:21 [PATCH] clk: imx8m: Use SYS_PLL1_800M as intermediate parent of CLK_ARM Leonard Crestez
2019-10-28  8:35 ` Shawn Guo
2019-10-28  9:45 ` Stephen Boyd

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