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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id t1sm4288687pgp.9.2019.10.29.10.24.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2019 10:24:33 -0700 (PDT) Date: Tue, 29 Oct 2019 10:24:31 -0700 From: Bjorn Andersson To: Will Deacon Subject: Re: [PATCH] arm64: cpufeature: Enable Qualcomm Falkor errata 1009 for Kryo Message-ID: <20191029172431.GY571@minitux> References: <20191029060604.1208925-1-bjorn.andersson@linaro.org> <20191029115008.GD12103@willie-the-truck> <16ccb343-8253-0224-e957-c73f51f110a1@codeaurora.org> <20191029171149.GB13281@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20191029171149.GB13281@willie-the-truck> User-Agent: Mutt/1.12.2 (2019-09-21) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191029_102436_029768_3957EE72 X-CRM114-Status: GOOD ( 22.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jeffrey Hugo , Catalin Marinas , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue 29 Oct 10:11 PDT 2019, Will Deacon wrote: > On Tue, Oct 29, 2019 at 09:07:53AM -0600, Jeffrey Hugo wrote: > > On 10/29/2019 7:44 AM, Jeffrey Hugo wrote: > > > On 10/29/2019 4:50 AM, Will Deacon wrote: > > > > On Mon, Oct 28, 2019 at 11:06:04PM -0700, Bjorn Andersson wrote: > > > > > The Kryo cores share errata 1009 with Falkor, so add their model > > > > > definitions and enable it for them as well. > > > > > = > > > > > Signed-off-by: Bjorn Andersson > > > > > --- > > > > > =A0 arch/arm64/include/asm/cputype.h | 4 ++++ > > > > > =A0 arch/arm64/kernel/cpu_errata.c=A0=A0 | 2 ++ > > > > > =A0 2 files changed, 6 insertions(+) > > > > > = > > > > > diff --git a/arch/arm64/include/asm/cputype.h > > > > > b/arch/arm64/include/asm/cputype.h > > > > > index b1454d117cd2..8067476ea2e4 100644 > > > > > --- a/arch/arm64/include/asm/cputype.h > > > > > +++ b/arch/arm64/include/asm/cputype.h > > > > > @@ -84,6 +84,8 @@ > > > > > =A0 #define QCOM_CPU_PART_FALKOR_V1=A0=A0=A0=A0=A0=A0=A0 0x800 > > > > > =A0 #define QCOM_CPU_PART_FALKOR=A0=A0=A0=A0=A0=A0=A0 0xC00 > > > > > =A0 #define QCOM_CPU_PART_KRYO=A0=A0=A0=A0=A0=A0=A0 0x200 > > > > > +#define QCOM_CPU_PART_KRYO_GOLD=A0=A0=A0=A0=A0=A0=A0 0x211 > > > > > +#define QCOM_CPU_PART_KRYO_SILVER=A0=A0=A0 0x205 > > > = > > > These are not Kryo part numbers (8998+).=A0 They are Hydra ones. > > > = > > > > = > > > > Can you double-check this, please? My Pixel-1 phone claims somethin= g with > > > > 0x201, but I don't know if that's what you were aiming for. It woul= d be > > > > great if Qualcomm could document these register fields somewhere, > > > > especially > > > > since we're trying to work around their hardware errata for them. > > > = > > > I wish I could point you to public documentation.=A0 I don't happen to > > > know where it is.=A0 As far as 8996 goes, there are quite a few part > > > numbers.=A0 The ones I could find are: > > > 201 > > > 205 > > > 211 > > > 241 > > > 251 > > > = > > > 281 happens to be QDF2432 > > = > > From asking around, I found someone in the know. We don't have public > > documentation, but I can follow up to try to create something - its lik= ely > > going to take a bit. I was given the following information to share. = This > > is specific to Hydra only- > > = > > MIDR[15:12] =3D PART[11:8] > > Hydra and technology node differentiator (0x1 =3D Hydra 16nm; 0x2 =3D H= ydra > > 14nm; 0x3 =3D Hydra 10nm) > > = > > MIDR[11:10] =3D PART[7:6] > > This corresponds to the cluster revision number > > = > > MIDR[9:8] =3D PART[5:4] > > Technology variant within the node > > = > > MIDR[7:6] =3D PART[3:2] > > 0b00 =3D 512KB L2 > > 0b01 =3D 1MB L2 > > 0b10 =3D 2MB L2 > > 0b11 =3D 4MB L2 > > = > > MIDR[5:4] =3D PART[1:0] > > 0b00 =3D uni-core > > 0b01 =3D dual-core cluster > > 0b10 =3D tri-core cluster > > 0b11 =3D quad-core cluster > = > Thanks for digging up the details, Jeffrey. As far as I can tell, our > 'is_kryo_midr()' function will return 'true' for all of these, so I think > that's what we should be using for this erratum workaround. Would that wo= rk > for you? > = Yes, I agree. There's a fair amount of variants involved, so let's go for is_kryo_midr() (which should be is_hydra_midr()). Regards, Bjorn _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel