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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Nov 04, 2019 at 07:20:58PM +0000, Will Deacon wrote: > On Mon, Nov 04, 2019 at 06:43:06PM +0000, Robin Murphy wrote: > > On 04/11/2019 18:20, Will Deacon wrote: > > > On Fri, Oct 25, 2019 at 07:08:36PM +0100, Robin Murphy wrote: > > > > Between VMSAv8-64 and the various 32-bit formats, there is either one > > > > 64-bit MAIR or a pair of 32-bit MAIR0/MAIR1 or NMRR/PMRR registers. > > > > As such, keeping two 64-bit values in io_pgtable_cfg has always been > > > > overkill. > > > > > > > > Signed-off-by: Robin Murphy > > > > --- > > > > drivers/iommu/arm-smmu-v3.c | 2 +- > > > > drivers/iommu/arm-smmu.c | 4 ++-- > > > > drivers/iommu/io-pgtable-arm.c | 3 +-- > > > > drivers/iommu/ipmmu-vmsa.c | 2 +- > > > > drivers/iommu/qcom_iommu.c | 4 ++-- > > > > include/linux/io-pgtable.h | 2 +- > > > > 6 files changed, 8 insertions(+), 9 deletions(-) > > > > > > > > diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c > > > > index 8da93e730d6f..3f20e548f1ec 100644 > > > > --- a/drivers/iommu/arm-smmu-v3.c > > > > +++ b/drivers/iommu/arm-smmu-v3.c > > > > @@ -2172,7 +2172,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, > > > > cfg->cd.asid = (u16)asid; > > > > cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; > > > > cfg->cd.tcr = pgtbl_cfg->arm_lpae_s1_cfg.tcr; > > > > - cfg->cd.mair = pgtbl_cfg->arm_lpae_s1_cfg.mair[0]; > > > > + cfg->cd.mair = pgtbl_cfg->arm_lpae_s1_cfg.mair; > > > > return 0; > > > > out_free_asid: > > > > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c > > > > index 080af0326816..2bc3e93b11e6 100644 > > > > --- a/drivers/iommu/arm-smmu.c > > > > +++ b/drivers/iommu/arm-smmu.c > > > > @@ -552,8 +552,8 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, > > > > cb->mair[0] = pgtbl_cfg->arm_v7s_cfg.prrr; > > > > cb->mair[1] = pgtbl_cfg->arm_v7s_cfg.nmrr; > > > > } else { > > > > - cb->mair[0] = pgtbl_cfg->arm_lpae_s1_cfg.mair[0]; > > > > - cb->mair[1] = pgtbl_cfg->arm_lpae_s1_cfg.mair[1]; > > > > + cb->mair[0] = pgtbl_cfg->arm_lpae_s1_cfg.mair; > > > > + cb->mair[1] = pgtbl_cfg->arm_lpae_s1_cfg.mair >> 32; > > > > > > Does this work correctly for big-endian? > > > > I don't see why it wouldn't - cfg.mair is read and written as a u64, so this > > should always return its most significant word regardless of the storage > > format. We're not doing anything dodgy like trying to type-pun the u64 > > directly into the u32[2]. > > Urgh, I need to convince myself about this then. Off to draw those silly > ABCD DCBA diagrams on some paper. Yes, you're right, it's fine. I was worried about explicitly writing 2x32-bit MAIRs and then loading them as one, but that's not what is going on here. Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel