From: Ard Biesheuvel <ardb@kernel.org>
To: linux-arm-kernel@lists.infradead.org
Cc: maz@kernel.org, rmk+kernel@armlinux.org.uk,
linus.walleij@linaro.org, Ard Biesheuvel <ardb@kernel.org>
Subject: [PATCH resend 2/2] Revert "ARM: 8857/1: efi: enable CP15 DMB instructions before cleaning the cache"
Date: Wed, 6 Nov 2019 11:49:18 +0100 [thread overview]
Message-ID: <20191106104918.26397-3-ardb@kernel.org> (raw)
In-Reply-To: <20191106104918.26397-1-ardb@kernel.org>
This reverts commit e17b1af96b2afc38e684aa2f1033387e2ed10029, which is
no longer necessary now that the v7 specific routines take care not to
issue CP15 barrier instructions before they are enabled in SCTLR.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
arch/arm/boot/compressed/head.S | 16 +---------------
1 file changed, 1 insertion(+), 15 deletions(-)
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index ec14687aea3c..4369f491b23d 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -1462,21 +1462,7 @@ ENTRY(efi_stub_entry)
@ Preserve return value of efi_entry() in r4
mov r4, r0
-
- @ our cache maintenance code relies on CP15 barrier instructions
- @ but since we arrived here with the MMU and caches configured
- @ by UEFI, we must check that the CP15BEN bit is set in SCTLR.
- @ Note that this bit is RAO/WI on v6 and earlier, so the ISB in
- @ the enable path will be executed on v7+ only.
- mrc p15, 0, r1, c1, c0, 0 @ read SCTLR
- tst r1, #(1 << 5) @ CP15BEN bit set?
- bne 0f
- orr r1, r1, #(1 << 5) @ CP15 barrier instructions
- mcr p15, 0, r1, c1, c0, 0 @ write SCTLR
- ARM( .inst 0xf57ff06f @ v7+ isb )
- THUMB( isb )
-
-0: bl cache_clean_flush
+ bl cache_clean_flush
bl cache_off
@ Set parameters for booting zImage according to boot protocol
--
2.17.1
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next prev parent reply other threads:[~2019-11-06 10:50 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-06 10:49 [PATCH resend 0/2] ARM/decompressor: deal with disabled CP15 barrier instructions Ard Biesheuvel
2019-11-06 10:49 ` [PATCH resend 1/2] ARM/decompressor: avoid CP15 barrier instructions in v7 cache setup code Ard Biesheuvel
2019-11-06 10:49 ` Ard Biesheuvel [this message]
2019-11-07 16:21 ` [PATCH resend 0/2] ARM/decompressor: deal with disabled CP15 barrier instructions Marc Zyngier
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