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Received: from shell.armlinux.org.uk ([2002:4e20:1eda:1:5054:ff:fe00:4ec]:34912) by pandora.armlinux.org.uk with esmtpsa (TLSv1.2:ECDHE-RSA-AES256-GCM-SHA384:256) (Exim 4.90_1) (envelope-from ) id 1iUpwJ-0003We-59; Wed, 13 Nov 2019 10:31:55 +0000 Received: from linux by shell.armlinux.org.uk with local (Exim 4.92) (envelope-from ) id 1iUpwF-0002NO-2l; Wed, 13 Nov 2019 10:31:51 +0000 Date: Wed, 13 Nov 2019 10:31:51 +0000 From: Russell King - ARM Linux admin To: Will Deacon Subject: Re: [PATCH v2] buffer: Fix I/O error due to ARM read-after-read hazard Message-ID: <20191113103150.GL25745@shell.armlinux.org.uk> References: <20191112130244.16630-1-vincent.whitchurch@axis.com> <20191112160855.GA22025@arrakis.emea.arm.com> <20191112180034.GB19889@willie-the-truck> <20191112182249.GB22025@arrakis.emea.arm.com> <20191113102357.GA25875@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20191113102357.GA25875@willie-the-truck> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191113_023212_011361_485CDDFB X-CRM114-Status: GOOD ( 14.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jens Axboe , Richard Earnshaw , Vincent Whitchurch , Catalin Marinas , Vincent Whitchurch , Linux Kernel Mailing List , Linus Torvalds , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Nov 13, 2019 at 10:23:58AM +0000, Will Deacon wrote: > On Tue, Nov 12, 2019 at 10:39:01AM -0800, Linus Torvalds wrote: > > On Tue, Nov 12, 2019 at 10:22 AM Catalin Marinas > > wrote: > > > > > > OK, so this includes changing test_bit() to perform a READ_ONCE. > > > > That's not going to happen. > > Ok, I'll stick my neck out here, but if test_bit() is being used to read > a bitmap that is being concurrently modified (e.g. by set_bit() which boils > down to atomic_long_or()), then why isn't READ_ONCE() required? Right now, > test_bit takes a 'const volatile unsigned long *addr' argument, so I don't > see that you'll get a change in codegen except on alpha and, with this > erratum, arm32. I'm not entirely clear what you're suggesting, so I'll just pick the scenario that I think you're talking about - but I'm not sure it's the one you're intending. Using test_bit() in one thread and set_bit() on the same bit in another thread without locking is going to be racy by definition. It's entirely possible for: Thread 1 Thread 2 bit = test_bit(...); set_bit(...); /* use bit */ and here, bit == 0 but the bit has been set by thread 2. Use of the result from test_bit() is inherently a non-atomic operation. This is why we have test_and_set_bit() and friends that atomically test that a bit is clear before setting it. Where this is especially important is for some filesystems, as they use test_and_xxx_bit() to manage their allocation bitmaps. -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up According to speedtest.net: 11.9Mbps down 500kbps up _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel