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Received: from shell.armlinux.org.uk ([fd8f:7570:feb6:1:5054:ff:fe00:4ec]:41676) by pandora.armlinux.org.uk with esmtpsa (TLSv1.2:ECDHE-RSA-AES256-GCM-SHA384:256) (Exim 4.90_1) (envelope-from ) id 1iX1D8-0000me-4N; Tue, 19 Nov 2019 10:58:18 +0000 Received: from linux by shell.armlinux.org.uk with local (Exim 4.92) (envelope-from ) id 1iX1D4-0000f2-UF; Tue, 19 Nov 2019 10:58:14 +0000 Date: Tue, 19 Nov 2019 10:58:14 +0000 From: Russell King - ARM Linux admin To: Marc Gonzalez Subject: Re: Using a GPIO as an interrupt line Message-ID: <20191119105814.GZ25745@shell.armlinux.org.uk> References: <20191119095748.GX25745@shell.armlinux.org.uk> <07db59e7-ff16-0457-87f2-fba10dc182d6@free.fr> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <07db59e7-ff16-0457-87f2-fba10dc182d6@free.fr> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191119_025827_447090_EF1BCF32 X-CRM114-Status: GOOD ( 22.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier , MSM , Linus Walleij , GPIO , Uwe Kleine-Konig , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Nov 19, 2019 at 11:46:21AM +0100, Marc Gonzalez wrote: > On 19/11/2019 10:57, Russell King - ARM Linux admin wrote: > > > On Tue, Nov 19, 2019 at 10:28:15AM +0100, Marc Gonzalez wrote: > > > >> The board I'm working on provides a TCA9539 I/O expander. > >> Or, as the datasheet(*) calls it, a "Low Voltage 16-Bit I2C and > >> SMBus Low-Power I/O Expander with Interrupt Output, Reset Pin, > >> and Configuration Registers" > >> > >> (*) http://www.ti.com/lit/ds/symlink/tca9539.pdf > >> > >> The binding is documented in Documentation/devicetree/bindings/gpio/gpio-pca953x.txt > >> > >> I have some doubts about the interrupt output, described as: > >> > >> Optional properties: > >> - interrupts: interrupt specifier for the device's interrupt output. > >> > >> In my board's DT, the I/O expander is described as: > >> > >> exp1: gpio@74 { > >> compatible = "ti,tca9539"; > >> reg = <0x74>; > >> gpio-controller; > >> #gpio-cells = <2>; > >> reset-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; > >> pinctrl-names = "default"; > >> pinctrl-0 = <&top_exp_rst>; > >> interrupt-parent = <&tlmm>; > >> interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; > > As pointed out by ukleinek on IRC, I might have (??) specified the wrong > trigger type. The data-sheet states: > "The TCA9539 open-drain interrupt (INTn) output is activated when any input state > differs from its corresponding Input Port register state, and is used to indicate > to the system master that an input state has changed." > (The data sheet speaks of "INT with a line on top"; what is the typical way to > write that in ASCII? I was told that adding a trailing 'n' or 'b' was common.) /INT or nINT are commonly used - I've never heard or seen 'b' (which is commonly used as a suffix on binary numbers) or a trailing 'n'. > According to that description, it looks like IRQ_TYPE_LEVEL_LOW? Yes. > > This specifies an interrupt signal, number 42, on the tlmm interrupt > > controller. It isn't a GPIO specification. Not every interrupt is a > > GPIO, and some SoCs can have dedicated interrupt pins that are > > exactly that. > > > > Hence, needlessly limiting an external device to requiring a GPIO for > > its interrupt is detrimental. > > That makes complete sense. > > IIUC, what is missing in my DT spec is defining pin 42 as a GPIO pin. > Looking more closely at top_exp_rst: > > top_exp_rst: top_exp_rst { > mux { > pins = "gpio96"; > function = "gpio"; > }; > > config { > pins = "gpio96"; > drive-strength = <2>; > bias-pull-down; > }; > }; > > IIUC, this defines pin 96 as a GPIO pin (as well as defining some low-level > properties of the pin). Likely I need something similar for pin 42? Is pin 42 something that can be muxed? If so, it seems sane to specify configuration for it. Whether it needs to be a GPIO or whether it has a specific "interrupt" function mux state depends on the SoC. For example, on the LX2160A, there are a bunch of pins that can be muxed as one of: - gpio - interrupt - something else -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up According to speedtest.net: 11.9Mbps down 500kbps up _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel