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Received: from shell.armlinux.org.uk ([2002:4e20:1eda:1:5054:ff:fe00:4ec]:38128) by pandora.armlinux.org.uk with esmtpsa (TLSv1.2:ECDHE-RSA-AES256-GCM-SHA384:256) (Exim 4.90_1) (envelope-from ) id 1iXTYi-0001Ck-Oq; Wed, 20 Nov 2019 17:14:28 +0000 Received: from linux by shell.armlinux.org.uk with local (Exim 4.92) (envelope-from ) id 1iXTYi-0001uc-0D; Wed, 20 Nov 2019 17:14:28 +0000 Date: Wed, 20 Nov 2019 17:14:27 +0000 From: Russell King - ARM Linux admin To: Leonid Movshovich Subject: Re: [PATCH] irq-gic: select all CPU's selected in interrupt affinity settings Message-ID: <20191120171427.GT25745@shell.armlinux.org.uk> References: <20191119233633.GG25745@shell.armlinux.org.uk> <2cd3e872-57d5-5cbb-78d7-98da6447dc59@arm.com> <392e74d78b48e04040cedfc26ed8ce81@www.loen.fr> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191120_091434_939348_A438911D X-CRM114-Status: GOOD ( 17.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier , Robin Murphy , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Nov 20, 2019 at 03:28:31PM +0000, Leonid Movshovich wrote: > On Wed, 20 Nov 2019 at 15:04, Marc Zyngier wrote: > > > > On 2019-11-20 01:15, Robin Murphy wrote: > > > On 2019-11-20 12:24 am, Leonid Movshovich wrote: > > >> On Tue, 19 Nov 2019 at 23:36, Russell King - ARM Linux admin > > >> wrote: > > >>> > > >>> On Tue, Nov 19, 2019 at 11:12:26PM +0000, event wrote: > > >>>> So far only a CPU selected with top affinity bit was selected. > > >>>> This > > >>>> resulted in all interrupts > > >>>> being processed by CPU0 by default despite "FF" default affinity > > >>>> setting for all interrupts > > >>> > > >>> Have you checked whether this causes _ALL_ CPUs in the mask to be > > >>> delivered a single interrupt, thereby causing _ALL_ CPUs to be > > >>> slowed down and hit the same locks at the same time. > > >>> > > >> Yes, I've checked this. No, interrupt is delivered to only one CPU. > > >> Also ARM GIC architecture specification specifically states in > > >> chapter > > >> 3.1.1 that hardware interrupts are delivered to a single CPU in > > >> multiprocessor system ("1-N model"). > > > > > > But see also section 3.2.3 - just because only one CPU actually runs > > > the given ISR doesn't necessarily guarantee that the others *weren't* > > > interrupted. I'd also hesitate to make any assumptions that all GIC > > > implementations behave exactly the same way. > > > > What happens is that *all* CPUs are being sent the interrupt, and there > > is some logic in the GIC that ensures that only one sees it (the first > > one to read the IAR register). All the other see a spurious (1023) > > interrupt, and have wasted some precious cycles in doing so. > > Cycles are only precious when system is under high load. Under high > load, to achieve fair spread of interrupts between CPUs one would need > a userspace app (irqbalance) to sit there and constantly rebalance > smp_affinity based on /proc/interrupts. Hard to believe such an > approach wastes less cycles. So you have no idea how irqbalance works... -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up According to speedtest.net: 11.9Mbps down 500kbps up _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel