From: Andre Przywara <andre.przywara@arm.com>
To: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org, linux-sunxi@googlegroups.com,
Rob Herring <robh+dt@kernel.org>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 0/3] arm/arm64: dts: allwinner: Add PMU nodes
Date: Thu, 21 Nov 2019 01:18:32 +0000 [thread overview]
Message-ID: <20191121011835.8467-1-andre.przywara@arm.com> (raw)
Arm Cortex cores contain a Performance Monitoring Unit (PMU), that needs
to be connected to the GIC distributor to be able to trigger interrupts.
The actual interrupt IDs are an integration choice, so need to be
advertised via the DT.
This series adds the DT nodes to the H3, H5 and H6 SoC .dtsi files.
The interrupt IDs are not always as described in the manual (off by 4
for the A64 and H5), so the IRQs have been both tested in U-Boot and
verified in Linux, using "perf record" (which requires working IRQs).
Cheers,
Andre.
Andre Przywara (3):
arm64: dts: allwinner: H6: Add PMU mode
arm64: dts: allwinner: H5: Add PMU node
arm: dts: allwinner: H3: Add PMU node
arch/arm/boot/dts/sun8i-h3.dtsi | 15 ++++++++++++---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 16 +++++++++++++---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++
3 files changed, 35 insertions(+), 6 deletions(-)
--
2.14.5
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next reply other threads:[~2019-11-21 1:18 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-21 1:18 Andre Przywara [this message]
2019-11-21 1:18 ` [PATCH 1/3] arm64: dts: allwinner: H6: Add PMU mode Andre Przywara
2019-11-21 7:22 ` Maxime Ripard
2019-11-21 9:25 ` Andre Przywara
2019-11-21 1:18 ` [PATCH 2/3] arm64: dts: allwinner: H5: Add PMU node Andre Przywara
2019-11-21 1:18 ` [PATCH 3/3] arm: dts: allwinner: H3: " Andre Przywara
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