From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Sven Auhagen <sven.auhagen@voleatech.de>
Cc: Baruch Siach <baruch@tkos.co.il>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: CP110 Comphy Issue
Date: Mon, 25 Nov 2019 16:12:08 +0100 [thread overview]
Message-ID: <20191125161208.750d583a@xps13> (raw)
In-Reply-To: <E5A2C8CE-447D-4FAB-A6A9-39F86146EBAF@voleatech.de>
Hi Sven,
> When I remove the PCIe card from CP1 the boot continues just fine.
Maybe you can have a look at the reset code.
Maybe also check the clock direction set in ATF -which might differ for
CP1 depending on the SaR registers.
> Also I looked through the code you probably want to change this, or you will try to access phys that are none for PCIes that have less than 4 lanes.
AFAIK this is not a problem but might be more elegant, please send a
patch to the ML.
Thanks,
Miquèl
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next prev parent reply other threads:[~2019-11-25 15:12 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-24 7:07 CP110 Comphy Issue Sven Auhagen
2019-11-24 7:31 ` Baruch Siach
2019-11-24 14:18 ` Miquel Raynal
2019-11-24 16:21 ` Sven Auhagen
2019-11-25 8:24 ` Sven Auhagen
2019-11-25 15:12 ` Miquel Raynal [this message]
[not found] <4EC81A7A-C1D1-4DDD-BD09-88D46BC0D058@voleatech.de>
2019-11-27 11:06 ` Miquel Raynal
2019-11-27 11:44 ` Sven Auhagen
2019-11-28 7:47 ` Sven Auhagen
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