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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Sven Auhagen <sven.auhagen@voleatech.de>
Cc: Baruch Siach <baruch@tkos.co.il>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: CP110 Comphy Issue
Date: Wed, 27 Nov 2019 12:06:18 +0100	[thread overview]
Message-ID: <20191127120618.66c46b7a@xps13> (raw)
In-Reply-To: <4EC81A7A-C1D1-4DDD-BD09-88D46BC0D058@voleatech.de>

Hi Sven,

Sven Auhagen <sven.auhagen@voleatech.de> wrote on Wed, 27 Nov 2019
06:08:16 +0000:

> Hi Miquèl,
> 
> I looked through the ATF code and as far as I can tell the pcie clock direction is set based on the sar register in cp110_pcie_clk_cfg
> I am not sure how this can lead to the problem of the comphy not coming up.

Clocks are often responsible of stalls when accessing registers.

I don't know what your problem is, I am giving you suggestions.

> I can also see that the PCIe works in uboot and the Intel NIC is recognized just fine there so the intial comphy setup must be working.

Is U-Boot doing SMC calls too? I suppose it does not.

> I could not find the reset code, can you send me the file where it is?

I thought we had some in the comphy driver, apparently not.

I don't have more inputs so far. Is your debugging giving interesting
infos? Have you checked in ->set_mode() everything looks fine?


Thanks,
Miquèl

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       reply	other threads:[~2019-11-27 11:06 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <4EC81A7A-C1D1-4DDD-BD09-88D46BC0D058@voleatech.de>
2019-11-27 11:06 ` Miquel Raynal [this message]
2019-11-27 11:44   ` CP110 Comphy Issue Sven Auhagen
2019-11-28  7:47   ` Sven Auhagen
2019-11-24  7:07 Sven Auhagen
2019-11-24  7:31 ` Baruch Siach
2019-11-24 14:18   ` Miquel Raynal
2019-11-24 16:21     ` Sven Auhagen
2019-11-25  8:24       ` Sven Auhagen
2019-11-25 15:12         ` Miquel Raynal

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