From: Michael Trimarchi <michael@amarulasolutions.com>
To: Shawn Guo <shawnguo@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
linux-amarula@amarulasolutions.com,
Sascha Hauer <s.hauer@pengutronix.de>,
linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
NXP Linux Team <linux-imx@nxp.com>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/3] arm64: dts: imx8mm: properly describe IRQ hierarchy
Date: Wed, 1 Jan 2020 17:31:36 +0100 [thread overview]
Message-ID: <20200101163136.1586-4-michael@amarulasolutions.com> (raw)
In-Reply-To: <20200101163136.1586-1-michael@amarulasolutions.com>
The GPCv2 sits between most of the peripherals and the GIC and
functions as a wakeup controller for the CPU cores. Add already
two power domains. Those domains was tested on imx8mm board
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 31 ++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 6edbdfe2d0d7..7360dc0685eb 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/clock/imx8mm-clock.h>
+#include <dt-bindings/power/imx8mm-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -12,7 +13,7 @@
#include "imx8mm-pinfunc.h"
/ {
- interrupt-parent = <&gic>;
+ interrupt-parent = <&gpc>;
#address-cells = <2>;
#size-cells = <2>;
@@ -197,6 +198,7 @@
interrupts = <GIC_PPI 7
(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
+ interrupt-parent = <&gic>;
};
timer {
@@ -206,6 +208,7 @@
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
clock-frequency = <8000000>;
+ interrupt-parent = <&gic>;
arm,no-tick-in-suspend;
};
@@ -498,6 +501,29 @@
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
+
+ gpc: gpc@303a0000 {
+ compatible = "fsl,imx8mm-gpc";
+ reg = <0x303a0000 0x10000>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ pgc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pgc_otg1: power-domain@2 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_USB_OTG1>;
+ };
+
+ pgc_otg2: power-domain@3 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_USB_OTG2>;
+ };
+ };
+ };
};
aips2: bus@30400000 {
@@ -790,6 +816,7 @@
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
fsl,usbphy = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
+ power-domains = <&pgc_otg1>;
status = "disabled";
};
@@ -809,6 +836,7 @@
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
fsl,usbphy = <&usbphynop2>;
fsl,usbmisc = <&usbmisc2 0>;
+ power-domains = <&pgc_otg2>;
status = "disabled";
};
@@ -856,6 +884,7 @@
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
};
ddr-pmu@3d800000 {
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-01-01 16:32 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-01 16:31 [PATCH 0/3] Add initial support for iMX8MM power domain Michael Trimarchi
2020-01-01 16:31 ` [PATCH 1/3] soc: imx: gpcv2: add support for i.MX8MM SoC Michael Trimarchi
2020-01-01 22:44 ` Adam Ford
2020-01-03 18:36 ` kbuild test robot
2020-01-01 16:31 ` [PATCH 2/3] irqchip/irq-imx-gpcv2: Add IRQCHIP_DECLARE for i.MX8MM compatible Michael Trimarchi
2020-01-01 16:31 ` Michael Trimarchi [this message]
2020-01-03 22:54 ` [PATCH 3/3] arm64: dts: imx8mm: properly describe IRQ hierarchy kbuild test robot
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200101163136.1586-4-michael@amarulasolutions.com \
--to=michael@amarulasolutions.com \
--cc=festevam@gmail.com \
--cc=kernel@pengutronix.de \
--cc=linux-amarula@amarulasolutions.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-imx@nxp.com \
--cc=linux-kernel@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=robh+dt@kernel.org \
--cc=s.hauer@pengutronix.de \
--cc=shawnguo@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).