From: Chen-Yu Tsai <wens@kernel.org>
To: Maxime Ripard <mripard@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org, Chen-Yu Tsai <wens@csie.org>,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 4/7] ARM: dts: sun8i: r40: Add device node for CSI0
Date: Mon, 6 Jan 2020 16:42:37 +0800 [thread overview]
Message-ID: <20200106084240.1076-5-wens@kernel.org> (raw)
In-Reply-To: <20200106084240.1076-1-wens@kernel.org>
From: Chen-Yu Tsai <wens@csie.org>
The CSI0 and CSI1 blocks are the same as found on the A20. However only
CSI0 is supported upstream right now.
Add a device node for CSI0 using the A20 compatible as a fallback, and
the standard pinctrl options. Also add the MBUS interconnect.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun8i-r40.dtsi | 36 ++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 7c940b20b81c..84d240c39f0f 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -181,6 +181,20 @@ nmi_intc: interrupt-controller@1c00030 {
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
+ csi0: csi@1c09000 {
+ compatible = "allwinner,sun8i-r40-csi0",
+ "allwinner,sun7i-a20-csi0";
+ reg = <0x01c09000 0x1000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>,
+ <&ccu CLK_DRAM_CSI0>;
+ clock-names = "bus", "isp", "ram";
+ resets = <&ccu RST_BUS_CSI0>;
+ interconnects = <&mbus 5>;
+ interconnect-names = "dma-mem";
+ status = "disabled";
+ };
+
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun8i-r40-mmc",
"allwinner,sun50i-a64-mmc";
@@ -356,6 +370,20 @@ clk_out_a_pin: clk-out-a-pin {
function = "clk_out_a";
};
+ /omit-if-no-ref/
+ csi0_8bits_pins: csi0-8bits-pins {
+ pins = "PE0", "PE2", "PE3", "PE4", "PE5",
+ "PE6", "PE7", "PE8", "PE9", "PE10",
+ "PE11";
+ function = "csi0";
+ };
+
+ /omit-if-no-ref/
+ csi0_mclk_pin: csi0-mclk-pin {
+ pins = "PE1";
+ function = "csi0";
+ };
+
gmac_rgmii_pins: gmac-rgmii-pins {
pins = "PA0", "PA1", "PA2", "PA3",
"PA4", "PA5", "PA6", "PA7",
@@ -625,6 +653,14 @@ gmac_mdio: mdio {
};
};
+ mbus: dram-controller@1c62000 {
+ compatible = "allwinner,sun8i-r40-mbus";
+ reg = <0x01c62000 0x1000>;
+ clocks = <&ccu 155>;
+ dma-ranges = <0x00000000 0x40000000 0x80000000>;
+ #interconnect-cells = <1>;
+ };
+
tcon_top: tcon-top@1c70000 {
compatible = "allwinner,sun8i-r40-tcon-top";
reg = <0x01c70000 0x1000>;
--
2.24.1
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next prev parent reply other threads:[~2020-01-06 8:43 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-06 8:42 [PATCH v2 0/7] media: sun4i-csi: A10/A20 CSI1 and R40 CSI0 support Chen-Yu Tsai
2020-01-06 8:42 ` [PATCH v2 1/7] ARM: dts: sun4i: Add CSI1 controller and pinmux options Chen-Yu Tsai
2020-01-06 8:42 ` [PATCH v2 2/7] ARM: dts: sun7i: " Chen-Yu Tsai
2020-01-06 8:42 ` [PATCH v2 3/7] dt-bindings: bus: sunxi: Add R40 MBUS compatible Chen-Yu Tsai
2020-01-06 8:51 ` Maxime Ripard
2020-03-12 5:36 ` Chen-Yu Tsai
2020-01-06 8:42 ` Chen-Yu Tsai [this message]
2020-01-06 8:42 ` [PATCH v2 5/7] [DO NOT MERGE] ARM: dts: sun4i: cubieboard: Enable OV7670 camera on CSI1 Chen-Yu Tsai
2020-01-06 8:42 ` [PATCH v2 6/7] [DO NOT MERGE] ARM: dts: sun7i: cubieboard2: " Chen-Yu Tsai
2020-01-06 8:42 ` [PATCH v2 7/7] [DO NOT MERGE] ARM: dts: sun8i-r40: bananapi-m2-ultra: Enable OV5640 camera Chen-Yu Tsai
2020-01-06 8:52 ` [PATCH v2 0/7] media: sun4i-csi: A10/A20 CSI1 and R40 CSI0 support Maxime Ripard
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