From: Kishon Vijay Abraham I <kishon@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Rob Herring <robh+dt@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
Andrew Murray <andrew.murray@arm.com>
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org
Subject: [PATCH v2 07/14] PCI: cadence: Allow pci_host_bridge to have custom pci_ops
Date: Mon, 6 Jan 2020 15:50:51 +0530 [thread overview]
Message-ID: <20200106102058.19183-8-kishon@ti.com> (raw)
In-Reply-To: <20200106102058.19183-1-kishon@ti.com>
Certain platforms like TI's J721E allows only 32-bit configuration
space access. In such cases pci_generic_config_read and
pci_generic_config_write cannot be used. Add support in Cadence core
to let pci_host_bridge have custom pci_ops.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/pci/controller/cadence/pcie-cadence-host.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index d6a38b74371c..29d3afd8cf06 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -288,7 +288,8 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
list_splice_init(&resources, &bridge->windows);
bridge->dev.parent = dev;
bridge->busnr = pcie->bus;
- bridge->ops = &cdns_pcie_host_ops;
+ if (!bridge->ops)
+ bridge->ops = &cdns_pcie_host_ops;
bridge->map_irq = of_irq_parse_and_map_pci;
bridge->swizzle_irq = pci_common_swizzle;
--
2.17.1
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next prev parent reply other threads:[~2020-01-06 10:21 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-06 10:20 [PATCH v2 00/14] Add PCIe support to TI's J721E SoC Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 01/14] dt-bindings: PCI: cadence: Add PCIe RC/EP DT schema for Cadence PCIe Kishon Vijay Abraham I
2020-01-08 3:43 ` Rob Herring
2020-01-08 5:35 ` Kishon Vijay Abraham I
2020-01-16 11:31 ` Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 02/14] PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 03/14] linux/kernel.h: Add PTR_ALIGN_DOWN macro Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 04/14] PCI: cadence: Add support to use custom read and write accessors Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 05/14] PCI: cadence: Add support to start link and verify link status Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 06/14] PCI: cadence: Add read/write accessors to perform only 32-bit accesses Kishon Vijay Abraham I
2020-01-06 10:20 ` Kishon Vijay Abraham I [this message]
2020-01-06 10:20 ` [PATCH v2 08/14] PCI: cadence: Add new *ops* for CPU addr fixup Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 09/14] PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 10/14] dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 11/14] dt-bindings: PCI: Add EP " Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 12/14] PCI: j721e: Add TI J721E PCIe driver Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 13/14] misc: pci_endpoint_test: Add J721E in pci_device_id table Kishon Vijay Abraham I
2020-01-06 10:20 ` [PATCH v2 14/14] MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe Kishon Vijay Abraham I
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