From: Shawn Guo <shawn.guo@linaro.org>
To: Vidya Sagar <vidyas@nvidia.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Jingoo Han <jingoohan1@gmail.com>,
linux-pci@vger.kernel.org,
Pratyush Anand <pratyush.anand@gmail.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Zaihai Yu <yuzaihai@hisilicon.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] PCI: dwc: Separate CFG0 and CFG1 into different ATU regions
Date: Fri, 10 Jan 2020 16:56:28 +0800 [thread overview]
Message-ID: <20200110085626.GA17787@T480> (raw)
In-Reply-To: <beda8923-a3b7-47eb-7cf1-19a3bacf1e34@nvidia.com>
Hi Vidya,
On Thu, Jan 09, 2020 at 11:04:01PM +0530, Vidya Sagar wrote:
>
>
> On 1/9/2020 11:36 AM, Shawn Guo wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > Some platform has 4 (or more) viewports. In that case, CFG0 and CFG1
> > can be separated into different ATU regions.
> Is there any specific benefit with this scheme?
Thanks much for the question which leads me to go back to vendor for
checking design details of 4 (or more) viewports.
It turns out the patch is not complete. We need more code change to
get the benefit of using separate ATU region for CFG0 and CFG1, that
is the dw_pcie_prog_outbound_atu() call in dw_pcie_access_other_conf()
function can be saved. But in the meanwhile, we need to pass
'va_cfg_base | busdev' as the first argument to dw_pcie_write/read()
in there.
@Lorenzo, @Bjorn,
Please ignore this patch.
Shawn
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prev parent reply other threads:[~2020-01-10 8:56 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-09 6:06 [PATCH] PCI: dwc: Separate CFG0 and CFG1 into different ATU regions Shawn Guo
2020-01-09 10:37 ` Gustavo Pimentel
2020-01-09 11:14 ` Shawn Guo
2020-01-09 11:28 ` Russell King - ARM Linux admin
2020-01-09 12:24 ` Gustavo Pimentel
2020-01-09 18:29 ` Bjorn Helgaas
2020-01-09 17:34 ` Vidya Sagar
2020-01-10 8:56 ` Shawn Guo [this message]
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