From: Will Deacon <will@kernel.org>
To: Pavel Tatashin <pasha.tatashin@soleen.com>
Cc: mark.rutland@arm.com, catalin.marinas@arm.com, stefan@agner.ch,
jmorris@namei.org, yamada.masahiro@socionext.com,
boris.ostrovsky@oracle.com, sashal@kernel.org,
sstabellini@kernel.org, maz@kernel.org, linux@armlinux.org.uk,
linux-arm-kernel@lists.infradead.org,
xen-devel@lists.xenproject.org, vladimir.murzin@arm.com,
julien@xen.org, alexios.zavras@intel.com, tglx@linutronix.de,
allison@lohutok.net, jgross@suse.com, steve.capper@arm.com,
gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org,
james.morse@arm.com, andrew.cooper3@citrix.com, info@metux.net
Subject: Re: [PATCH v5 3/6] arm64: remove uaccess_ttbr0 asm macros from cache functions
Date: Tue, 14 Jan 2020 18:14:41 +0000 [thread overview]
Message-ID: <20200114181440.GH2579@willie-the-truck> (raw)
In-Reply-To: <20200102211357.8042-4-pasha.tatashin@soleen.com>
On Thu, Jan 02, 2020 at 04:13:54PM -0500, Pavel Tatashin wrote:
> We currently duplicate the logic to enable/disable uaccess via TTBR0,
> with C functions and assembly macros. This is a maintenenace burden
> and is liable to lead to subtle bugs, so let's get rid of the assembly
> macros, and always use the C functions. This requires refactoring
> some assembly functions to have a C wrapper.
>
> Signed-off-by: Pavel Tatashin <pasha.tatashin@soleen.com>
> ---
> arch/arm64/include/asm/asm-uaccess.h | 22 ----------------
> arch/arm64/include/asm/cacheflush.h | 39 +++++++++++++++++++++++++---
> arch/arm64/mm/cache.S | 36 ++++++++++---------------
> arch/arm64/mm/flush.c | 2 +-
> 4 files changed, 50 insertions(+), 49 deletions(-)
>
> diff --git a/arch/arm64/include/asm/asm-uaccess.h b/arch/arm64/include/asm/asm-uaccess.h
> index f68a0e64482a..fba2a69f7fef 100644
> --- a/arch/arm64/include/asm/asm-uaccess.h
> +++ b/arch/arm64/include/asm/asm-uaccess.h
> @@ -34,28 +34,6 @@
> msr ttbr0_el1, \tmp1 // set the non-PAN TTBR0_EL1
> isb
> .endm
> -
> - .macro uaccess_ttbr0_disable, tmp1, tmp2
> -alternative_if_not ARM64_HAS_PAN
> - save_and_disable_irq \tmp2 // avoid preemption
> - __uaccess_ttbr0_disable \tmp1
> - restore_irq \tmp2
> -alternative_else_nop_endif
> - .endm
> -
> - .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3
> -alternative_if_not ARM64_HAS_PAN
> - save_and_disable_irq \tmp3 // avoid preemption
> - __uaccess_ttbr0_enable \tmp1, \tmp2
> - restore_irq \tmp3
> -alternative_else_nop_endif
> - .endm
> -#else
> - .macro uaccess_ttbr0_disable, tmp1, tmp2
> - .endm
> -
> - .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3
> - .endm
> #endif
>
> #endif
> diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h
> index 665c78e0665a..cb00c61e0bde 100644
> --- a/arch/arm64/include/asm/cacheflush.h
> +++ b/arch/arm64/include/asm/cacheflush.h
> @@ -61,16 +61,49 @@
> * - kaddr - page address
> * - size - region size
> */
> -extern void __flush_icache_range(unsigned long start, unsigned long end);
> -extern int invalidate_icache_range(unsigned long start, unsigned long end);
> +extern void __asm_flush_icache_range(unsigned long start, unsigned long end);
> +extern long __asm_flush_cache_user_range(unsigned long start,
> + unsigned long end);
> +extern int __asm_invalidate_icache_range(unsigned long start,
> + unsigned long end);
> extern void __flush_dcache_area(void *addr, size_t len);
> extern void __inval_dcache_area(void *addr, size_t len);
> extern void __clean_dcache_area_poc(void *addr, size_t len);
> extern void __clean_dcache_area_pop(void *addr, size_t len);
> extern void __clean_dcache_area_pou(void *addr, size_t len);
> -extern long __flush_cache_user_range(unsigned long start, unsigned long end);
> extern void sync_icache_aliases(void *kaddr, unsigned long len);
>
> +static inline long __flush_cache_user_range(unsigned long start,
> + unsigned long end)
> +{
> + int ret;
> +
> + uaccess_ttbr0_enable();
> + ret = __asm_flush_cache_user_range(start, end);
> + uaccess_ttbr0_disable();
> +
> + return ret;
> +}
> +
> +static inline void __flush_icache_range(unsigned long start, unsigned long end)
> +{
> + uaccess_ttbr0_enable();
> + __asm_flush_icache_range(start, end);
> + uaccess_ttbr0_disable();
> +}
Interesting... I don't think we should be enabling uaccess here: the
function has a void return type so we can't communicate failure back to the
caller if we fault, so my feeling is that this should only ever be called on
kernel addresses.
> +
> +static inline int invalidate_icache_range(unsigned long start,
> + unsigned long end)
> +{
> + int ret;
> +
> + uaccess_ttbr0_enable();
> + ret = __asm_invalidate_icache_range(start, end);
> + uaccess_ttbr0_disable();
> +
> + return ret;
> +}
Same here -- I don't think think this is ever called on user addresses.
Can we make the return type void and drop the uaccess toggle?
Will
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next prev parent reply other threads:[~2020-01-14 18:14 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-02 21:13 [PATCH v5 0/6] Use C inlines for uaccess Pavel Tatashin
2020-01-02 21:13 ` [PATCH v5 1/6] arm/arm64/xen: hypercall.h add includes guards Pavel Tatashin
2020-01-06 17:18 ` Stefano Stabellini
2020-01-08 17:59 ` Pavel Tatashin
2020-01-02 21:13 ` [PATCH v5 2/6] arm/arm64/xen: use C inlines for privcmd_call Pavel Tatashin
2020-01-02 21:13 ` [PATCH v5 3/6] arm64: remove uaccess_ttbr0 asm macros from cache functions Pavel Tatashin
2020-01-14 18:14 ` Will Deacon [this message]
2020-01-02 21:13 ` [PATCH v5 4/6] arm64: remove __asm_flush_icache_range Pavel Tatashin
2020-01-02 21:13 ` [PATCH v5 5/6] arm64: move ARM64_HAS_CACHE_DIC/_IDC from asm to C Pavel Tatashin
2020-01-14 18:26 ` Will Deacon
2020-01-02 21:13 ` [PATCH v5 6/6] arm64: remove the rest of asm-uaccess.h Pavel Tatashin
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