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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jan 02, 2020 at 04:13:56PM -0500, Pavel Tatashin wrote: > The assmbly functions __asm_flush_cache_user_range and > __asm_invalidate_icache_range have alternatives: > > alternative_if ARM64_HAS_CACHE_DIC > ... > > alternative_if ARM64_HAS_CACHE_IDC > ... > > But, the implementation of those alternatives is trivial and therefore > can be done in the C inline wrappers. > > Signed-off-by: Pavel Tatashin > --- > arch/arm64/include/asm/cacheflush.h | 19 +++++++++++++++++++ > arch/arm64/mm/cache.S | 27 +++++---------------------- > arch/arm64/mm/flush.c | 1 + > 3 files changed, 25 insertions(+), 22 deletions(-) > > diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h > index 047af338ba15..fc5217a18398 100644 > --- a/arch/arm64/include/asm/cacheflush.h > +++ b/arch/arm64/include/asm/cacheflush.h > @@ -77,8 +77,22 @@ static inline long __flush_cache_user_range(unsigned long start, > { > int ret; > > + if (cpus_have_const_cap(ARM64_HAS_CACHE_IDC)) { > + dsb(ishst); > + if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC)) { > + isb(); > + return 0; > + } > + } > + > uaccess_ttbr0_enable(); > ret = __asm_flush_cache_user_range(start, end); I don't understand this. Doesn't it mean a CPU with IDC but not DIC will end up with doing the D-cache maintenance? Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel