* [PATCH stable 4.9] arm64: kpti: Whitelist Cortex-A CPUs that don't implement the CSV3 field
@ 2020-01-24 20:08 Florian Fainelli
2020-01-28 8:08 ` Greg KH
0 siblings, 1 reply; 2+ messages in thread
From: Florian Fainelli @ 2020-01-24 20:08 UTC (permalink / raw)
To: linux-arm-kernel
Cc: sashal, Florian Fainelli, Suzuki K Poulose, gregkh, Will Deacon,
open list, stable, Catalin Marinas, will
From: Will Deacon <will.deacon@arm.com>
commit 2a355ec25729053bb9a1a89b6c1d1cdd6c3b3fb1 upstream.
While the CSV3 field of the ID_AA64_PFR0 CPU ID register can be checked
to see if a CPU is susceptible to Meltdown and therefore requires kpti
to be enabled, existing CPUs do not implement this field.
We therefore whitelist all unaffected Cortex-A CPUs that do not implement
the CSV3 field.
Signed-off-by: Will Deacon <will.deacon@arm.com>
[florian: adjust whilelist location and table to stable-4.9.y]
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm64/kernel/cpufeature.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 9a8e45dc36bd..8cf001baee21 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -789,6 +789,11 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
switch (read_cpuid_id() & MIDR_CPU_MODEL_MASK) {
case MIDR_CAVIUM_THUNDERX2:
case MIDR_BRCM_VULCAN:
+ case MIDR_CORTEX_A53:
+ case MIDR_CORTEX_A55:
+ case MIDR_CORTEX_A57:
+ case MIDR_CORTEX_A72:
+ case MIDR_CORTEX_A73:
return false;
}
--
2.17.1
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^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH stable 4.9] arm64: kpti: Whitelist Cortex-A CPUs that don't implement the CSV3 field
2020-01-24 20:08 [PATCH stable 4.9] arm64: kpti: Whitelist Cortex-A CPUs that don't implement the CSV3 field Florian Fainelli
@ 2020-01-28 8:08 ` Greg KH
0 siblings, 0 replies; 2+ messages in thread
From: Greg KH @ 2020-01-28 8:08 UTC (permalink / raw)
To: Florian Fainelli
Cc: sashal, Suzuki K Poulose, Catalin Marinas, Will Deacon, open list,
stable, will, linux-arm-kernel
On Fri, Jan 24, 2020 at 12:08:20PM -0800, Florian Fainelli wrote:
> From: Will Deacon <will.deacon@arm.com>
>
> commit 2a355ec25729053bb9a1a89b6c1d1cdd6c3b3fb1 upstream.
>
> While the CSV3 field of the ID_AA64_PFR0 CPU ID register can be checked
> to see if a CPU is susceptible to Meltdown and therefore requires kpti
> to be enabled, existing CPUs do not implement this field.
>
> We therefore whitelist all unaffected Cortex-A CPUs that do not implement
> the CSV3 field.
>
> Signed-off-by: Will Deacon <will.deacon@arm.com>
> [florian: adjust whilelist location and table to stable-4.9.y]
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Thanks for the backport, now applied.
greg k-h
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