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Received: from shell.armlinux.org.uk ([2001:4d48:ad52:3201:5054:ff:fe00:4ec]:60650) by pandora.armlinux.org.uk with esmtpsa (TLSv1.2:ECDHE-RSA-AES256-GCM-SHA384:256) (Exim 4.90_1) (envelope-from ) id 1iw8cW-0002lu-E0; Mon, 27 Jan 2020 17:56:20 +0000 Received: from linux by shell.armlinux.org.uk with local (Exim 4.92) (envelope-from ) id 1iw8cS-0001bc-5y; Mon, 27 Jan 2020 17:56:16 +0000 Date: Mon, 27 Jan 2020 17:56:16 +0000 From: Russell King - ARM Linux admin To: Andrew Lunn Subject: Re: [RFC net-next 6/8] net: phylink: Configure MAC/PCS when link is up without PHY Message-ID: <20200127175616.GZ25745@shell.armlinux.org.uk> References: <9a2136885d9a892ff170be88fdffeda82c778a10.1580122909.git.Jose.Abreu@synopsys.com> <20200127112102.GT25745@shell.armlinux.org.uk> <20200127114600.GU25745@shell.armlinux.org.uk> <20200127140038.GD13647@lunn.ch> <20200127140834.GW25745@shell.armlinux.org.uk> <20200127145107.GE13647@lunn.ch> <20200127161132.GX25745@shell.armlinux.org.uk> <20200127163241.GK13647@lunn.ch> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200127163241.GK13647@lunn.ch> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200127_095640_933567_68CD39A7 X-CRM114-Status: GOOD ( 19.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jose Abreu , Joao Pinto , Alexandre Torgue , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "David S. Miller" , Florian Fainelli , Maxime Coquelin , Giuseppe Cavallaro , Jakub Kicinski , "linux-stm32@st-md-mailman.stormreply.com" , "linux-arm-kernel@lists.infradead.org" , Heiner Kallweit Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jan 27, 2020 at 05:32:41PM +0100, Andrew Lunn wrote: > > Presumably, all these should be visible on the ZII rev B as well? > > Maybe. The two SFF mounted on most rev B are connected to ports which > only do SGMII, not 1000Base X. They tend to work by chance, and as > such, i've never taken them seriously. > > If i remember correctly, you modified your board, moved the SFF over > to the normally unpopulated slots, and removed a resistor. That setup > then has the SFF connected to the 6352, which can do both SGMII and > 1000BaseX. Yes, I modified the board to fix a design mistake - removing R412. The SFF are where they are when they were delivered: OPT P1 - no module fitted, and the serdes signals are not routed. This might as well not exist. OPT P2 - Cotsworks SFBG53DRAP. This is connected to port 4 of switch 0, one of the 88E6352. The 88E6352 can have the serdes block associated with either port 4 or port 5 depending on the state of the S_SEL signal. The serdes will be associated with port 4 if S_SEL is low at reset, and with port 5 if S_SEL is high at reset. 88E6352 Port 4 RGMII signals are not used. Port 5 RGMII is used to connect to the next 88E6352 switch. So, if the serdes is associated with port 5, and if RGMII is used, it prevents the use of the serdes. With R412 fitted, S_SEL is pulled high, and assocates the serdes with port 5, and hence is unusable. When R412 is removed, the serdes is associated with port 4, and can be configured for either SGMII or 1000baseX mode via the PHY detect bit. So, the ZII rev B, OPT P2 only becomes useful if R412 is removed. OPT P3 - Cotsworks SFBG53DRAP This is connected to port 3 of switch 2, one of the 88E6185. OPT P4 - AVAGO AFBR-59R5ALZ This is connected to port 4 of switch 2, one of the 88E6185. The 88E6185 can only have ports 7, 8 or 9 configured for 1000BASE-X mode. These two ports end up configured for cross-chip serdes mode which is 1000BASE-X but with manually controlled link status, as this mode is designed to link two 88E6185 to each other (hence "cross-chip"). There appears to be no accessible serdes block on this device to give us any interrupts. With my suggestion for a polling mode in phylink, it may be possible to get OPT P3 and OPT P4 working. > It could also be that the 6352 does have pass through from the PCS to > the MAC, where as the 6390 does not? The 6390 is much more capable, > having 2.5G and 10G support. The SERDES registers are very different, > C45 vs C22 of the 6352. My feeling is that the issues you're seeing with the ZII rev C come down to the phylink implementation for MV88E6xxx lacking some of the necessary support, and this has probably been broken ever since phylink was introduced into the mainline MV88E6xxx driver. Try http://git.armlinux.org.uk/cgit/linux-arm.git/patch/?id=eb717ca455b1ae425a4d4b60615ba3e4d0ba35d4 which will be 5.4 based; I haven't pushed out my 5.5 based tree yet as I'm busy writing emails rather than testing it, and running out of time to do so before tomorrow! -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up According to speedtest.net: 11.9Mbps down 500kbps up _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel