linux-arm-kernel.lists.infradead.org archive mirror
 help / color / mirror / Atom feed
From: Marc Zyngier <maz@kernel.org>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
	Gavin Shan <gshan@redhat.com>,
	Beata Michalska <beata.michalska@linaro.org>,
	kvm@vger.kernel.org, Will Deacon <will@kernel.org>,
	kvmarm@lists.cs.columbia.edu, YueHaibing <yuehaibing@huawei.com>,
	Steven Price <steven.price@arm.com>,
	Zenghui Yu <yuzenghui@huawei.com>,
	Haibin Wang <wanghaibin.wang@huawei.com>,
	Julien Thierry <julien.thierry.kdev@gmail.com>,
	Andrew Jones <drjones@redhat.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Shannon Zhao <shannon.zhao@linux.alibaba.com>,
	Eric Auger <eric.auger@redhat.com>,
	Russell King <rmk+kernel@armlinux.org.uk>,
	Mark Brown <broonie@kernel.org>,
	Alexandru Elisei <alexandru.elisei@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	Christoffer Dall <christoffer.dall@arm.com>,
	James Morse <james.morse@arm.com>,
	Andrew Murray <andrew.murray@arm.com>
Subject: [PATCH 21/23] KVM: arm64: pmu: Fix chained SW_INCR counters
Date: Thu, 30 Jan 2020 13:25:56 +0000	[thread overview]
Message-ID: <20200130132558.10201-22-maz@kernel.org> (raw)
In-Reply-To: <20200130132558.10201-1-maz@kernel.org>

From: Eric Auger <eric.auger@redhat.com>

At the moment a SW_INCR counter always overflows on 32-bit
boundary, independently on whether the n+1th counter is
programmed as CHAIN.

Check whether the SW_INCR counter is a 64b counter and if so,
implement the 64b logic.

Fixes: 80f393a23be6 ("KVM: arm/arm64: Support chained PMU counters")
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200124142535.29386-4-eric.auger@redhat.com
---
 virt/kvm/arm/pmu.c | 43 ++++++++++++++++++++++++++++++-------------
 1 file changed, 30 insertions(+), 13 deletions(-)

diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index 9f605e0b8dd7..560db6282137 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -477,28 +477,45 @@ static void kvm_pmu_perf_overflow(struct perf_event *perf_event,
  */
 void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val)
 {
+	struct kvm_pmu *pmu = &vcpu->arch.pmu;
 	int i;
-	u64 type, enable, reg;
-
-	if (val == 0)
-		return;
 
 	if (!(__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E))
 		return;
 
-	enable = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
+	/* Weed out disabled counters */
+	val &= __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
+
 	for (i = 0; i < ARMV8_PMU_CYCLE_IDX; i++) {
+		u64 type, reg;
+
 		if (!(val & BIT(i)))
 			continue;
-		type = __vcpu_sys_reg(vcpu, PMEVTYPER0_EL0 + i)
-		       & ARMV8_PMU_EVTYPE_EVENT;
-		if ((type == ARMV8_PMUV3_PERFCTR_SW_INCR)
-		    && (enable & BIT(i))) {
-			reg = __vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) + 1;
+
+		/* PMSWINC only applies to ... SW_INC! */
+		type = __vcpu_sys_reg(vcpu, PMEVTYPER0_EL0 + i);
+		type &= ARMV8_PMU_EVTYPE_EVENT;
+		if (type != ARMV8_PMUV3_PERFCTR_SW_INCR)
+			continue;
+
+		/* increment this even SW_INC counter */
+		reg = __vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) + 1;
+		reg = lower_32_bits(reg);
+		__vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) = reg;
+
+		if (reg) /* no overflow on the low part */
+			continue;
+
+		if (kvm_pmu_pmc_is_chained(&pmu->pmc[i])) {
+			/* increment the high counter */
+			reg = __vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i + 1) + 1;
 			reg = lower_32_bits(reg);
-			__vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) = reg;
-			if (!reg)
-				__vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= BIT(i);
+			__vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i + 1) = reg;
+			if (!reg) /* mark overflow on the high counter */
+				__vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= BIT(i + 1);
+		} else {
+			/* mark overflow on low counter */
+			__vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= BIT(i);
 		}
 	}
 }
-- 
2.20.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2020-01-30 13:32 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-30 13:25 [GIT PULL 00/23] KVM/arm updates for 5.6 Marc Zyngier
2020-01-30 13:25 ` [PATCH 01/23] KVM: arm64: Only sign-extend MMIO up to register width Marc Zyngier
2020-01-30 13:25 ` [PATCH 02/23] KVM: arm/arm64: vgic-its: Fix restoration of unmapped collections Marc Zyngier
2020-01-30 13:25 ` [PATCH 03/23] KVM: arm/arm64: vgic: Handle GICR_PENDBASER.PTZ filed as RAZ Marc Zyngier
2020-01-30 13:25 ` [PATCH 04/23] arm64: kvm: Fix IDMAP overlap with HYP VA Marc Zyngier
2020-01-30 13:25 ` [PATCH 05/23] KVM: ARM: Call hyp_cpu_pm_exit at the right place Marc Zyngier
2020-01-30 13:25 ` [PATCH 06/23] KVM: arm: Remove duplicate include Marc Zyngier
2020-01-30 13:25 ` [PATCH 07/23] KVM: arm/arm64: Re-check VMA on detecting a poisoned page Marc Zyngier
2020-01-30 13:25 ` [PATCH 08/23] KVM: arm64: Correct PSTATE on exception entry Marc Zyngier
2020-01-30 13:25 ` [PATCH 09/23] KVM: arm/arm64: Correct CPSR " Marc Zyngier
2020-01-30 13:25 ` [PATCH 10/23] KVM: arm/arm64: Correct AArch32 SPSR " Marc Zyngier
2020-01-30 13:25 ` [PATCH 11/23] KVM: arm/arm64: vgic-its: Properly check the unmapped coll in DISCARD handler Marc Zyngier
2020-01-30 13:25 ` [PATCH 12/23] KVM: arm/arm64: vgic: Drop the kvm_vgic_register_mmio_region() Marc Zyngier
2020-01-30 13:25 ` [PATCH 13/23] KVM: arm/arm64: Cleanup MMIO handling Marc Zyngier
2020-01-30 13:25 ` [PATCH 14/23] arm64: KVM: Add UAPI notes for swapped registers Marc Zyngier
2020-01-30 13:25 ` [PATCH 15/23] arm64: KVM: Annotate guest entry/exit as a single function Marc Zyngier
2020-01-30 13:25 ` [PATCH 16/23] KVM: arm/arm64: Fix young bit from mmu notifier Marc Zyngier
2020-01-30 13:25 ` [PATCH 17/23] KVM: arm: Fix DFSR setting for non-LPAE aarch32 guests Marc Zyngier
2020-01-30 13:25 ` [PATCH 18/23] KVM: arm: Make inject_abt32() inject an external abort instead Marc Zyngier
2020-01-30 13:25 ` [PATCH 19/23] KVM: arm64: pmu: Don't increment SW_INCR if PMCR.E is unset Marc Zyngier
2020-01-30 13:25 ` [PATCH 20/23] KVM: arm64: pmu: Don't mark a counter as chained if the odd one is disabled Marc Zyngier
2020-01-30 13:25 ` Marc Zyngier [this message]
2020-01-30 13:25 ` [PATCH 22/23] KVM: arm64: pmu: Only handle supported event counters Marc Zyngier
2020-01-30 13:25 ` [PATCH 23/23] KVM: arm64: Treat emulated TVAL TimerValue as a signed 32-bit integer Marc Zyngier
2020-01-30 14:11   ` Alexandru Elisei
2020-01-30 14:15     ` Marc Zyngier
2020-01-30 17:13 ` [GIT PULL 00/23] KVM/arm updates for 5.6 Paolo Bonzini

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200130132558.10201-22-maz@kernel.org \
    --to=maz@kernel.org \
    --cc=alexandru.elisei@arm.com \
    --cc=andrew.murray@arm.com \
    --cc=beata.michalska@linaro.org \
    --cc=broonie@kernel.org \
    --cc=christoffer.dall@arm.com \
    --cc=drjones@redhat.com \
    --cc=eric.auger@redhat.com \
    --cc=gshan@redhat.com \
    --cc=james.morse@arm.com \
    --cc=julien.thierry.kdev@gmail.com \
    --cc=kvm@vger.kernel.org \
    --cc=kvmarm@lists.cs.columbia.edu \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=mark.rutland@arm.com \
    --cc=pbonzini@redhat.com \
    --cc=rmk+kernel@armlinux.org.uk \
    --cc=shannon.zhao@linux.alibaba.com \
    --cc=steven.price@arm.com \
    --cc=suzuki.poulose@arm.com \
    --cc=wanghaibin.wang@huawei.com \
    --cc=will@kernel.org \
    --cc=yuehaibing@huawei.com \
    --cc=yuzenghui@huawei.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).