[PATCH 0/1] Xilinx Zynq Ultrascale+ MPSoc CoreSight DT nodes

From: "Wojciech Żmuda" <wzmuda@n7space.com>
To: "linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"coresight@lists.linaro.org" <coresight@lists.linaro.org>
Cc: "mark.rutland@arm.com" <mark.rutland@arm.com>,
	"mathieu.poirier@linaro.org" <mathieu.poirier@linaro.org>,
	"rajan.vaja@xilinx.com" <rajan.vaja@xilinx.com>,
	"Michal Mosdorf" <mmosdorf@n7space.com>,
	"antoine.tenart@bootlin.com" <antoine.tenart@bootlin.com>,
	"nava.manne@xilinx.com" <nava.manne@xilinx.com>,
	"michal.simek@xilinx.com" <michal.simek@xilinx.com>,
	"m.tretter@pengutronix.de" <m.tretter@pengutronix.de>,
	"t-kristo@ti.com" <t-kristo@ti.com>,
	"Krzysztof Pilch" <kpilch@n7space.com>,
	"Wojciech Żmuda" <wzmuda@n7space.com>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"Michał Kurowski" <mkurowski@n7space.com>
Subject: [PATCH 0/1] Xilinx Zynq Ultrascale+ MPSoc CoreSight DT nodes
Date: Thu, 30 Jan 2020 15:36:24 +0000	[thread overview]
Message-ID: <20200130153613.20365-1-wzmuda@n7space.com> (raw)

From: Wojciech Zmuda <wzmuda@n7space.com>

This patch adds CoreSight nodes to Zynq US+ device tree. I tested in on
recent v5.5 tree, on Xilinx ZCU104 development board.

Tracing with perf:
   root@zynq:~# perf record -e cs_etm/timestamp,cycacc,@tmc_etr0/u true
   Couldn't synthesize bpf events.
   [ perf record: Woken up 1 times to write data ]
   [ perf record: Captured and wrote 0.073 MB perf.data ]

   root@zynq:~# perf report --dump | grep "CoreSight ETM Trace data" -A10
   . ... CoreSight ETM Trace data: size 74112 bytes
           Idx:0; ID:14;   I_ASYNC : Alignment Synchronisation.
           Idx:12; ID:14;  I_TRACE_INFO : Trace Info.; INFO=0x1 { CC.1 }; CC_THRESHOLD=0x100
           Idx:19; ID:14;  I_ADDR_L_64IS0 : Address, Long, 64 bit, IS0.; Addr=0xFFFF800010839BF8;
           Idx:28; ID:14;  I_TRACE_ON : Trace On.
           Idx:29; ID:14;  I_ADDR_CTXT_L_64IS0 : Address & Context, Long, 64 bit, IS0.; Addr=0x0000FFFF83F37080; Ctxt: AArch64,EL0, NS; CID=0x00000281;
           Idx:44; ID:14;  I_ATOM_F1 : Atom format 1.; E
           Idx:45; ID:14;  I_CCNT_F1 : Cycle Count format 1.; Count=0x0
           Idx:46; ID:14;  I_TIMESTAMP : Timestamp.; Updated val = 0x29aa0b739ec; CC=0x1
           Idx:58; ID:14;  I_EXCEPT : Exception.;  Data Fault; Ret Addr Follows;
           Idx:60; ID:14;  I_ADDR_L_64IS0 : Address, Long, 64 bit, IS0.; Addr=0x0000FFFF83F37964;

Please note that to get non-zero timestamps on this platform, the timestamp
generator module needs to be explicitly enabled, e.g. from U-Boot, by writing
'1' to 0xfe900000.

Debug components:
   root@zynq:~# echo 1 > /sys/kernel/debug/coresight_cpu_debug/enable
   root@zynq:~# echo c > /proc/sysrq-trigger
   [   57.5093] ARM external debug module:
   [   57.513099] coresight-cpu-deb fec10000.debug0: CPU[0]:
   [   57.518407] coresight-cpu-debug fec10000.debug0:  EDPRSR:  00000001 (Power:On DLK:Unlock
                                                                                              [   57.526583] coresight-cpu-debug fec10000.debug0:  EDPCSR: ocal_cpu_stop+0x2c/0x38
   [   57.534236] coresight-cpu-debug fec10000.debug0:  EDCIDSR: 00000000
   [   57.540494] coresit-cpu-debug fec10000.debug0:  EDVIDSR: 90000000 (State:Non-sece Mode:EL1/0 Width:64bits VMID:0)
   [   57.551095] coresight-cpu-debug fed10000.debug1: CPU[1]:
   [   57.556406] coresig-cpu-debug fed10000.debug1:  EDPRSR:  00000001 (Power:On DLK:Uock)
   [   57.564584] coresight-cpu-debug fed10000.debug1:  EDPCSR:  local_cpu_stop+0x2c/0x38
   [   57.572237] coresightpu-debug fed10000.debug1:  EDCIDSR: 00000000
   [   57.578494] cesight-cpu-debug fed10000.debug1:  EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
   [   57.589096]oresight-cpu-debug fee10000.debug2: CPU[2]:
   [   57.594408] cosight-cpu-debug fee10000.debug2:  EDPRSR:  00000001 (Power:On DLK:Unlock)
   [   57.602587] coresight-cpu-debug fee10000ebug2:  EDPCSR:  debug_notifier_call+0x2b8/0x3b0
   [   57.61084 coresight-cpu-debug fee10000.debug2:  EDCIDSR: 00000170
   [   57.617103] coresight-cpu-debug fee10000.debug2:  EDVIDSR90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
   [ 57.627705] coresight-cpu-debug fef10000.debug3: CPU[3]:
   [   57.633016] coresight-cpu-debug fef10000.debug3:  EDPRSR: 0000001 (Power:On DLK:Unlock)
   [   57.641193] coresight-cpu-deg fef10000.debug3:  EDPCSR:  local_cpu_stop+0x2c/0x38
   [   57.648846] coresight-cpu-debug fef10000.debug3:  EDCIDSR: 000000
   [   57.655104] coresight-cpu-debug fef10000.debug3:  EDDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
   [   57.665708] Rebooting in 60 seconds..

Wojciech Zmuda (1):
  arm64: zynqmp: Add CoreSight components

 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi | 272 +++++++++++++++++++++++
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi           |   2 +
 2 files changed, 274 insertions(+)
 create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-coresight.dtsi

-- 
2.11.0

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