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Received: from shell.armlinux.org.uk ([2001:4d48:ad52:3201:5054:ff:fe00:4ec]:35968) by pandora.armlinux.org.uk with esmtpsa (TLSv1.2:ECDHE-RSA-AES256-GCM-SHA384:256) (Exim 4.90_1) (envelope-from ) id 1iz3w3-00040d-Fm; Tue, 04 Feb 2020 19:32:35 +0000 Received: from linux by shell.armlinux.org.uk with local (Exim 4.92) (envelope-from ) id 1iz3vy-0001AI-Sy; Tue, 04 Feb 2020 19:32:30 +0000 Date: Tue, 4 Feb 2020 19:32:30 +0000 From: Russell King - ARM Linux admin To: Andrew Lunn Subject: Re: [RFC net-next 6/8] net: phylink: Configure MAC/PCS when link is up without PHY Message-ID: <20200204193230.GT25745@shell.armlinux.org.uk> References: <20200127114600.GU25745@shell.armlinux.org.uk> <20200127140038.GD13647@lunn.ch> <20200127140834.GW25745@shell.armlinux.org.uk> <20200127145107.GE13647@lunn.ch> <20200127161132.GX25745@shell.armlinux.org.uk> <20200127162206.GJ13647@lunn.ch> <20200204172603.GS25745@shell.armlinux.org.uk> <20200204174318.GB1364@lunn.ch> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200204174318.GB1364@lunn.ch> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200204_113254_223766_95FB7891 X-CRM114-Status: GOOD ( 21.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jose Abreu , Joao Pinto , Alexandre Torgue , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "David S. Miller" , Florian Fainelli , Maxime Coquelin , Giuseppe Cavallaro , Jakub Kicinski , "linux-stm32@st-md-mailman.stormreply.com" , "linux-arm-kernel@lists.infradead.org" , Heiner Kallweit Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Feb 04, 2020 at 06:43:18PM +0100, Andrew Lunn wrote: > > There, there is one MAC, but there are multiple different PCS - one > > for SGMII and 1000base-X, another for 10G, another for 25G, etc. > > These PCS are accessed via a MDIO adapter embedded in each of the > > MAC hardware blocks. > > Hi Russell > > Marvell mv88e6390X switches are like this is a well. There is a PCS > for SGMII and 1000Base-X, and a second one for 10G. And it dynamically > swaps between them depending on the port mode, the so called cmode. > > So a generic solution is required, and please take your time to build > one. Well, DSA is quite a mixed bag... As far as I can work out, the situation with the CPU and DSA ports is quite hopeless - you've claimed that a change in phylink has broken it, I can't find what that may be. The fact is, phylink has never had any link information for DSA links when no fixed-link property has been specified in DT. As I've already said in a previous email about this, I can't see *any* sane way to fix that - but there was no response. On a more positive note... The mac_link_up() changes that I've talked about should work for DSA, if only there was a reasonable way to reconfigure the ports. If you look at the "phy" branch, you will notice that there's a patch there - "net: mv88e6xxx: use resolved link config in mac_link_up()" which adds the support to configure the MAC manually. It's rather messy, and I see no way to deal with the pause settings. There is support in some Marvell DSA switches to force flow control but that's not supported through the current mid-layer at all (port_set_pause doesn't do it.) I'm not sure whether the "mv88e6xxx_phy_is_internal()" check there is the right test for every DSA switch correct either. What is missing is reading the results from the PCS (aka serdes) and forwarding them into phylink - I did have a quick look at how that might be possible, but the DSA code structure (consisting of multiple mid-layers) makes it hard without rewriting quite a lot of code. That's fine if you know all the DSA chips inside out, but I don't - and that's where we need someone who has the knowledge of all DSA switches that we support. Or, we get rid of the multiple mid-layers and switch to a library approach, so that we can modify support for one DSA switch without affecting everything. It may be a simple matter of dropping the existing serdes workaround, but I'm not sure at the moment. I've tried this code out on the ZII rev B, I haven't tried it on the rev C which has the 6390 switches yet. -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up According to speedtest.net: 11.9Mbps down 500kbps up _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel