From: Fabio Estevam <festevam@gmail.com>
To: shawnguo@kernel.org
Cc: sboyd@kernel.org, linux-imx@nxp.com, kernel@pengutronix.de,
Fabio Estevam <festevam@gmail.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/2] clk: imx8mm: Fix the CLKO1 source select list
Date: Tue, 11 Feb 2020 00:08:12 -0300 [thread overview]
Message-ID: <20200211030813.13992-1-festevam@gmail.com> (raw)
The CLKO1 clock source select list is the following as per the i.MX8MM
Reference Manual (put in increasing order):
000 - 24M_REF_CLK
001 - SYSTEM_PLL1_CLK
010 - None
011 - SYSTEM_PLL1_DIV4
100 - AUDIO_PLL2_CLK
101 - SYSTEM_PLL2_DIV2
110 - VPU_PLL_CLK
111 - SYSTEM_PLL1_DIV10
Fix it accordingly.
Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
drivers/clk/imx/clk-imx8mm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 2ed93fc25087..770cf2ae58aa 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -283,8 +283,8 @@ static const char *imx8mm_vpu_h1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_8
static const char *imx8mm_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
-static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m", "sys_pll1_200m", "audio_pll2_out",
- "vpu_pll", "sys_pll1_80m", };
+static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "dummy", "sys_pll1_200m",
+ "audio_pll2_out", "sys_pll2_500m", "vpu_pll", "sys_pll1_80m", };
static struct clk_hw_onecell_data *clk_hw_data;
static struct clk_hw **hws;
--
2.17.1
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next reply other threads:[~2020-02-11 3:09 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-11 3:08 Fabio Estevam [this message]
2020-02-11 3:08 ` [PATCH 2/2] clk: imx8mm: Add CLKO2 support Fabio Estevam
2020-02-11 7:18 ` [PATCH 1/2] clk: imx8mm: Fix the CLKO1 source select list Abel Vesa
2020-02-17 5:50 ` Shawn Guo
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