From: Will Deacon <will@kernel.org>
To: Joakim Zhang <qiangqing.zhang@nxp.com>
Cc: mark.rutland@arm.com, robin.murphy@arm.com, linux-imx@nxp.com,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/2] perf/imx_ddr: Correct the CLEAR bit definition
Date: Mon, 2 Mar 2020 11:25:34 +0000 [thread overview]
Message-ID: <20200302112534.GC7995@willie-the-truck> (raw)
In-Reply-To: <20200225125644.18853-1-qiangqing.zhang@nxp.com>
On Tue, Feb 25, 2020 at 08:56:43PM +0800, Joakim Zhang wrote:
> ddr_perf_event_stop will firstly call ddr_perf_counter_enable to disable
> the counter, and then call ddr_perf_event_update to read the counter value.
>
> When disable the counter, it will write 0 into COUNTER_CNTL[CLEAR] bit
> which cause the counter value cleared. Counter value will always be 0
> when update the counter.
>
> The correct definition of CLEAR bit is that write 0 to clear the counter
> value.
Ok, so the issue is that when disabling the counter we clear the counter
value at the same time. I'll update the text and apply this fix.
Cheers,
Will
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next prev parent reply other threads:[~2020-03-02 11:25 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-25 12:56 [PATCH 1/2] perf/imx_ddr: Correct the CLEAR bit definition Joakim Zhang
2020-02-25 12:56 ` [PATCH 2/2] perf/imx_ddr: Add stop counter support for i.MX8MP Joakim Zhang
2020-03-02 11:24 ` Will Deacon
2020-03-03 5:34 ` Joakim Zhang
2020-04-16 9:51 ` Joakim Zhang
2020-05-20 7:51 ` Will Deacon
2020-05-21 4:57 ` Joakim Zhang
2020-03-02 11:25 ` Will Deacon [this message]
2020-03-03 5:34 ` [PATCH 1/2] perf/imx_ddr: Correct the CLEAR bit definition Joakim Zhang
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