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[217.229.22.169]) by smtp.gmail.com with ESMTPSA id b203sm5222572wme.32.2020.03.10.10.10.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2020 10:10:25 -0700 (PDT) Date: Tue, 10 Mar 2020 18:10:25 +0100 From: Thierry Reding To: Dmitry Osipenko Subject: Re: [PATCH v5 3/8] clk: tegra: Implement Tegra210 EMC clock Message-ID: <20200310171025.GD3079591@ulmo> References: <20200310152003.2945170-1-thierry.reding@gmail.com> <20200310152003.2945170-4-thierry.reding@gmail.com> <88d18719-b6dd-98d0-e147-f89eed2f3f0c@gmail.com> MIME-Version: 1.0 In-Reply-To: <88d18719-b6dd-98d0-e147-f89eed2f3f0c@gmail.com> User-Agent: Mutt/1.13.1 (2019-12-14) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200310_101028_812200_CF813393 X-CRM114-Status: GOOD ( 15.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Stephen Boyd , Michael Turquette , Jon Hunter , Rob Herring , Joseph Lo , linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: multipart/mixed; boundary="===============5208538451546616606==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============5208538451546616606== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="bjuZg6miEcdLYP6q" Content-Disposition: inline --bjuZg6miEcdLYP6q Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Mar 10, 2020 at 07:26:28PM +0300, Dmitry Osipenko wrote: > 10.03.2020 18:19, Thierry Reding =D0=BF=D0=B8=D1=88=D0=B5=D1=82: > > From: Joseph Lo > >=20 > > The EMC clock needs to carefully coordinate with the EMC controller > > programming to make sure external memory can be properly clocked. Do so > > by hooking up the EMC clock with an EMC provider that will specify which > > rates are supported by the EMC and provide a callback to use for setting > > the clock rate at the EMC. > >=20 > > Based on work by Peter De Schrijver . > >=20 > > Signed-off-by: Joseph Lo > > Signed-off-by: Thierry Reding > > --- > > Changes in v5: > > - major rework and cleanup >=20 > ... >=20 > > +u32 emc_readl(struct tegra_emc *emc, unsigned long offset) > > +{ > > + return readl_relaxed(emc->emc_base[REG_EMC] + offset); > > +} >=20 > static u32 emc_readl() >=20 > > +u32 emc_readl_per_ch(struct tegra_emc *emc, int type, > > + unsigned long offset) >=20 > static u32 emc_readl_per_ch() I think something went wrong here during a rebase. These are actually supposed to be part of the EMC driver patch and are no longer needed in the clock driver. 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