[PATCH 1/2] ARM: dts: imx6: phycore-som: explicit disable pmic watchdog during suspend

[PATCH 1/2] ARM: dts: imx6: phycore-som: explicit disable pmic watchdog during suspend

[Marco Felsch]

By default the phycore-som has support for two watchdog devices: 1st the
internal imx6 watchdog and 2nd the DA9062 PMIC watchdog. According [1]
the PMIC watchdog is used as boot watchdog. It is common to use this
watchdog during "system up" time too. Furthermore the PMIC watchdog can
be used to address ERR007117 since the phycore-som can be equipped with
NAND or eMMC storage.

The PMIC watchdog can be enabled/disabled by the PMIC itself if the PMIC
enters POWERDOWN mode or by the host. The PMIC powerdown mode can't be
used due to the PCB design. So the watchdog is still enabled during a
suspend which causes a system reset. We need to tell the driver to
disable the watchdog during a system suspend and to reenable it upon a
resume to fix this.

[1] https://git.pengutronix.de/cgit/barebox/tree/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi#n73

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
Hi,

I tested it on a with a phycore imx6q other testers are welcome =)
The binding landed in v5.6-rc1 and the driver handling in v5.6-rc3.

Regards,
  Marco

 arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
index 77d871340eb7..8b71bf33ba30 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
@@ -107,6 +107,7 @@
 
 		watchdog {
 			compatible = "dlg,da9062-watchdog";
+			dlg,use-sw-pm;
 		};
 
 		regulators {
-- 
2.20.1


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[PATCH 2/2] ARM: dts: imx6: phycore-som: add da9062 gpio support

[Marco Felsch]

The pmic is a mfd device and supports gpios. Those gpios are not routed
to the SoM baseboard pin header but they are connected to the i.MX6. We
need the GPIO's to configure the pmic to select between the
suspend/resume arm and soc voltages

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

 arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
index 8b71bf33ba30..41ebe4599e43 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
@@ -88,7 +88,7 @@
 		reg = <0x50>;
 	};
 
-	pmic@58 {
+	pmic: pmic@58 {
 		compatible = "dlg,da9062";
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_pmic>;
@@ -96,6 +96,8 @@
 		interrupt-parent = <&gpio1>;
 		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
 		interrupt-controller;
+		gpio-controller;
+		#gpio-cells = <2>;
 
 		da9062_rtc: rtc {
 			compatible = "dlg,da9062-rtc";
-- 
2.20.1


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Re: [PATCH 1/2] ARM: dts: imx6: phycore-som: explicit disable pmic watchdog during suspend

[Shawn Guo]

On Thu, Feb 27, 2020 at 12:06:04PM +0100, Marco Felsch wrote:
> By default the phycore-som has support for two watchdog devices: 1st the
> internal imx6 watchdog and 2nd the DA9062 PMIC watchdog. According [1]
> the PMIC watchdog is used as boot watchdog. It is common to use this
> watchdog during "system up" time too. Furthermore the PMIC watchdog can
> be used to address ERR007117 since the phycore-som can be equipped with
> NAND or eMMC storage.
> 
> The PMIC watchdog can be enabled/disabled by the PMIC itself if the PMIC
> enters POWERDOWN mode or by the host. The PMIC powerdown mode can't be
> used due to the PCB design. So the watchdog is still enabled during a
> suspend which causes a system reset. We need to tell the driver to
> disable the watchdog during a system suspend and to reenable it upon a
> resume to fix this.
> 
> [1] https://git.pengutronix.de/cgit/barebox/tree/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi#n73
> 
> Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>

Applied, thanks.

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Re: [PATCH 2/2] ARM: dts: imx6: phycore-som: add da9062 gpio support

[Shawn Guo]

On Thu, Feb 27, 2020 at 12:06:05PM +0100, Marco Felsch wrote:
> The pmic is a mfd device and supports gpios. Those gpios are not routed
> to the SoM baseboard pin header but they are connected to the i.MX6. We
> need the GPIO's to configure the pmic to select between the
> suspend/resume arm and soc voltages
> 
> Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
> 
>  arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)

Not sure why this is here.  I removed it and applied the patch.

Shawn

> 
> diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
> index 8b71bf33ba30..41ebe4599e43 100644
> --- a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
> @@ -88,7 +88,7 @@
>  		reg = <0x50>;
>  	};
>  
> -	pmic@58 {
> +	pmic: pmic@58 {
>  		compatible = "dlg,da9062";
>  		pinctrl-names = "default";
>  		pinctrl-0 = <&pinctrl_pmic>;
> @@ -96,6 +96,8 @@
>  		interrupt-parent = <&gpio1>;
>  		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
>  		interrupt-controller;
> +		gpio-controller;
> +		#gpio-cells = <2>;
>  
>  		da9062_rtc: rtc {
>  			compatible = "dlg,da9062-rtc";
> -- 
> 2.20.1
> 

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