[PATCH net-next v4 05/11] dt-binding: ti: am65x: document mcu cpsw nuss

Grygorii Strashko
2020-03-17T07:29:30Z

Document device tree bindings for The TI AM654x/J721E SoC Gigabit Ethernet MAC
(Media Access Controller - CPSW2G NUSS). The CPSW NUSS provides Ethernet packet
communication for the device.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
---
.../bindings/net/ti,k3-am654-cpsw-nuss.yaml | 226 ++++++++++++++++++
1 file changed, 226 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml

diff --git a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
new file mode 100644
index 000000000000..c28b5c925377
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
@@ -0,0 +1,226 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: The TI AM654x/J721E SoC Gigabit Ethernet MAC (Media Access Controller) Device Tree Bindings
+
+maintainers:
+ - Grygorii Strashko <grygorii.strashko@ti.com>
+ - Sekhar Nori <nsekhar@ti.com>
+
+description:
+ The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports
+ (one external) and provides Ethernet packet communication for the device.
+ CPSW2G NUSS features - the Reduced Gigabit Media Independent Interface (RGMII),
+ Reduced Media Independent Interface (RMII), the Management Data
+ Input/Output (MDIO) interface for physical layer device (PHY) management,
+ new version of Common Platform Time Sync (CPTS), updated Address Lookup
+ Engine (ALE).
+ One external Ethernet port (port 1) with selectable RGMII/RMII interfaces and
+ an internal Communications Port Programming Interface (CPPI5) (Host port 0).
+ Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels
+ and one RX channels and operating by TI AM654x/J721E NAVSS Unified DMA
+ Peripheral Root Complex (UDMA-P) controller.
+ The CPSW2G NUSS is integrated into device MCU domain named MCU_CPSW0.
+
+ Additional features
+ priority level Quality Of Service (QOS) support (802.1p)
+ Support for Audio/Video Bridging (P802.1Qav/D6.0)
+ Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F)
+ Flow Control (802.3x) Support
+ Time Sensitive Network Support
+ IEEE P902.3br/D2.0 Interspersing Express Traffic
+ IEEE 802.1Qbv/D2.2 Enhancements for Scheduled Traffic
+ Configurable number of addresses plus VLANs
+ Configurable number of classifier/policers
+ VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on
+ ingress, Auto VLAN removal on egress and auto pad to minimum frame size.
+ RX/TX csum offload
+
+ Specifications can be found at
+ http://www.ti.com/lit/ug/spruid7e/spruid7e.pdf
+ http://www.ti.com/lit/ug/spruil1a/spruil1a.pdf
+
+properties:
+ "#address-cells": true
+ "#size-cells": true
+
+ compatible:
+ oneOf:
+ - const: ti,am654-cpsw-nuss
+ - const: ti,j721e-cpsw-nuss
+
+ reg:
+ maxItems: 1
+ description:
+ The physical base address and size of full the CPSW2G NUSS IO range
+
+ reg-names:
+ items:
+ - const: cpsw_nuss
+
+ ranges: true
+
+ dma-coherent: true
+
+ clocks:
+ description: CPSW2G NUSS functional clock
+
+ clock-names:
+ items:
+ - const: fck
+
+ power-domains:
+ maxItems: 1
+
+ dmas:
+ minItems: 9
+ maxItems: 9
+
+ dma-names:
+ items:
+ - const: tx0
+ - const: tx1
+ - const: tx2
+ - const: tx3
+ - const: tx4
+ - const: tx5
+ - const: tx6
+ - const: tx7
+ - const: rx
+
+ pinctrl-names: true
+
+ ethernet-ports:
+ type: object
+ properties:
+ '#address-cells':
+ const: 1
+ '#size-cells':
+ const: 0
+
+ patternProperties:
+ "^port@[0-9]+$":
+ type: object
+ description: CPSW2G NUSS external ports
+
+ allOf:
+ - $ref: ethernet-controller.yaml#
+
+ properties:
+ reg:
+ items:
+ - const: 1
+ description: CPSW port number
+
+ phys:
+ maxItems: 1
+ description: phandle on phy-gmii-sel PHY
+
+ label:
+ description: label associated with this port
+
+ ti,mac-only:
+ $ref: /schemas/types.yaml#definitions/flag
+ description:
+ Specifies the port works in mac-only mode.
+
+ ti,syscon-efuse:
+ $ref: /schemas/types.yaml#definitions/phandle-array
+ description:
+ Phandle to the system control device node which provides access
+ to efuse IO range with MAC addresses
+
+ required:
+ - reg
+ - phys
+
+ mdio:
+ type: object
+ allOf:
+ - $ref: "ti,davinci-mdio.yaml#"
+ description:
+ CPSW MDIO bus.
+
+patternProperties:
+ "^pinctrl-[0-9]+$": true
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - ranges
+ - clocks
+ - clock-names
+ - power-domains
+ - dmas
+ - dma-names
+ - '#address-cells'
+ - '#size-cells'
+
+examples:
+ - |
+ #include <dt-bindings/pinctrl/k3.h>
+ #include <dt-bindings/soc/ti,sci_pm_domain.h>
+ #include <dt-bindings/net/ti-dp83867.h>
+
+ mcu_cpsw: ethernet@46000000 {
+ compatible = "ti,am654-cpsw-nuss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x46000000 0x0 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x0 0x0 0x46000000 0x0 0x200000>;
+ dma-coherent;
+ clocks = <&k3_clks 5 10>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+
+ dmas = <&mcu_udmap 0xf000>,
+ <&mcu_udmap 0xf001>,
+ <&mcu_udmap 0xf002>,
+ <&mcu_udmap 0xf003>,
+ <&mcu_udmap 0xf004>,
+ <&mcu_udmap 0xf005>,
+ <&mcu_udmap 0xf006>,
+ <&mcu_udmap 0xf007>,
+ <&mcu_udmap 0x7000>;
+ dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
+ "rx";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw_port1: port@1 {
+ reg = <1>;
+ ti,mac-only;
+ label = "port1";
+ ti,syscon-efuse = <&mcu_conf 0x200>;
+ phys = <&phy_gmii_sel 1>;
+
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&phy0>;
+ };
+ };
+
+ davinci_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x0 0xf00 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 5 10>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+ };
+ };