From: Shawn Guo <shawnguo@kernel.org>
To: Waibel Georg <Georg.Waibel@wiedemann-group.com>
Cc: Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
NXP Linux Team <linux-imx@nxp.com>,
Michel Alex <Alex.Michel@wiedemann-group.com>,
Appelt Andreas <Andreas.Appelt@wiedemann-group.com>,
Sascha Hauer <s.hauer@pengutronix.de>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH] clk: imx: imx6ul: change flexcan clock to support CiA bitrates
Date: Tue, 17 Mar 2020 21:48:13 +0800 [thread overview]
Message-ID: <20200317134810.GA2884@dragon> (raw)
In-Reply-To: <1584352708854.43164@wiedemann-group.com>
On Mon, Mar 16, 2020 at 09:58:28AM +0000, Waibel Georg wrote:
> On Mon, 16 Mar 2020 at 02:30, Shawn Guo <shawnguo@kernel.org> wrote:
> > On Wed, Mar 11, 2020 at 12:03:40PM +0000, Waibel Georg wrote:
> > > Setting a CAN bitrate of 800kbit/s fails with a bitrate error of 1.3% if the
> > > flexcan module is clocked at 30MHz (CAN_CLK_ROOT). This patch changes the clock
> > > frequency from 30MHz to 40MHz which allows to support all bitrates recommended
> >
> > But code changes IMX6UL_CLK_PLL3_60M to IMX6UL_CLK_PLL3_80M? Or
> > IMX6UL_CLK_CAN_SEL is different from CAN_CLK_ROOT in the context?
>
> Correct. The patch sets CAN_CLK_SEL to 80MHZ. There is a post-divider
> CAN_CLK_PODF which is set to /2 by default which makes the 40MHz
> CAN_CLK_ROOT.
Could you add this into commit log to make it clear?
Shawn
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next prev parent reply other threads:[~2020-03-17 13:48 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-11 12:03 [PATCH] clk: imx: imx6ul: change flexcan clock to support CiA bitrates Waibel Georg
2020-03-16 1:30 ` Shawn Guo
2020-03-16 9:55 ` AW: " Waibel Georg
2020-03-16 9:58 ` Waibel Georg
2020-03-17 13:48 ` Shawn Guo [this message]
2020-03-18 10:33 ` [PATCH V2] " Waibel Georg
2020-04-13 14:22 ` Shawn Guo
2024-06-28 8:08 ` Random flexcan probe error on i.MX6ULL after flexcan clock increase Enguerrand de Ribaucourt
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