* [PATCH] clk: imx: imx6ul: change flexcan clock to support CiA bitrates
@ 2020-03-11 12:03 Waibel Georg
2020-03-16 1:30 ` Shawn Guo
0 siblings, 1 reply; 8+ messages in thread
From: Waibel Georg @ 2020-03-11 12:03 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Shawn Guo, Sascha Hauer,
NXP Linux Team, linux-arm-kernel@lists.infradead.org
Cc: Michel Alex, Appelt Andreas
Setting a CAN bitrate of 800kbit/s fails with a bitrate error of 1.3% if the
flexcan module is clocked at 30MHz (CAN_CLK_ROOT). This patch changes the clock
frequency from 30MHz to 40MHz which allows to support all bitrates recommended
by CiA.
Background:
CAN in Automation document 102 (CiA102) recommends the CAN bitrates 10, 20, 50,
125, 250, 500, 800 and 1000kbit/s.
With the flexcan serial clock at 30MHz (original value) setting some common
bitrates ("ip link set canX type can bitrate <bitrate>") gives the following
results:
requested value / actually set value
5000: bitrate 5000 sample-point 0.708
10000: bitrate 10000 sample-point 0.866
20000: bitrate 20000 sample-point 0.866
40000: bitrate 40000 sample-point 0.866
50000: bitrate 50000 sample-point 0.866
80000: bitrate 80000 sample-point 0.866
100000: bitrate 100000 sample-point 0.866
125000: bitrate 125000 sample-point 0.875
250000: bitrate 250000 sample-point 0.866
400000: bitrate 400000 sample-point 0.866
500000: bitrate 500000 sample-point 0.866
666666: bitrate 666666 sample-point 0.800
800000: bitrate 789473 sample-point 0.789 !!!bitrate error 1.3%
1000000: bitrate 1000000 sample-point 0.733
With the flexcan serial clock at 40MHz (new value) we get this:
5000: no more possible
10000: bitrate 10000 sample-point 0.875
20000: bitrate 20000 sample-point 0.875
40000: bitrate 40000 sample-point 0.850
50000: bitrate 50000 sample-point 0.875
80000: bitrate 80000 sample-point 0.850
100000: bitrate 100000 sample-point 0.875
125000: bitrate 125000 sample-point 0.875
250000: bitrate 250000 sample-point 0.875
400000: bitrate 400000 sample-point 0.850
500000: bitrate 500000 sample-point 0.875
666666: bitrate 666666 sample-point 0.800
800000: bitrate 800000 sample-point 0.800
1000000: bitrate 1000000 sample-point 0.750
A drawback of the modification is that 5kbit/s is no more supported.
Setting the flexcan serial clock to 60MHz or 80MHz would produce similar
results but with losing even more bitrates at the lower end.
Changing the flexcan serial clock to 40MHz might apply for other SoCs
using the flaxcan module as well (e.g. imx6q/d/s..). But since I don't
have such hardware to test I did not add this to the patch.
Signed-off-by: Georg Waibel <georg.waibel@wiedemann-group.de>
---
drivers/clk/imx/clk-imx6ul.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index dafc8806b03e..5dbb6a937732 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -503,7 +503,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
clk_prepare_enable(hws[IMX6UL_CLK_USBPHY2_GATE]->clk);
}
- clk_set_parent(hws[IMX6UL_CLK_CAN_SEL]->clk, hws[IMX6UL_CLK_PLL3_60M]->clk);
+ clk_set_parent(hws[IMX6UL_CLK_CAN_SEL]->clk, hws[IMX6UL_CLK_PLL3_80M]->clk);
if (clk_on_imx6ul())
clk_set_parent(hws[IMX6UL_CLK_SIM_PRE_SEL]->clk, hws[IMX6UL_CLK_PLL3_USB_OTG]->clk);
else if (clk_on_imx6ull())
--
2.17.1
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^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH] clk: imx: imx6ul: change flexcan clock to support CiA bitrates
2020-03-11 12:03 [PATCH] clk: imx: imx6ul: change flexcan clock to support CiA bitrates Waibel Georg
@ 2020-03-16 1:30 ` Shawn Guo
2020-03-16 9:55 ` AW: " Waibel Georg
0 siblings, 1 reply; 8+ messages in thread
From: Shawn Guo @ 2020-03-16 1:30 UTC (permalink / raw)
To: Waibel Georg
Cc: Stephen Boyd, Michael Turquette, NXP Linux Team, Michel Alex,
Appelt Andreas, Sascha Hauer,
linux-arm-kernel@lists.infradead.org
On Wed, Mar 11, 2020 at 12:03:40PM +0000, Waibel Georg wrote:
> Setting a CAN bitrate of 800kbit/s fails with a bitrate error of 1.3% if the
> flexcan module is clocked at 30MHz (CAN_CLK_ROOT). This patch changes the clock
> frequency from 30MHz to 40MHz which allows to support all bitrates recommended
But code changes IMX6UL_CLK_PLL3_60M to IMX6UL_CLK_PLL3_80M? Or
IMX6UL_CLK_CAN_SEL is different from CAN_CLK_ROOT in the context?
Shawn
> by CiA.
>
> Background:
> CAN in Automation document 102 (CiA102) recommends the CAN bitrates 10, 20, 50,
> 125, 250, 500, 800 and 1000kbit/s.
>
> With the flexcan serial clock at 30MHz (original value) setting some common
> bitrates ("ip link set canX type can bitrate <bitrate>") gives the following
> results:
> requested value / actually set value
> 5000: bitrate 5000 sample-point 0.708
> 10000: bitrate 10000 sample-point 0.866
> 20000: bitrate 20000 sample-point 0.866
> 40000: bitrate 40000 sample-point 0.866
> 50000: bitrate 50000 sample-point 0.866
> 80000: bitrate 80000 sample-point 0.866
> 100000: bitrate 100000 sample-point 0.866
> 125000: bitrate 125000 sample-point 0.875
> 250000: bitrate 250000 sample-point 0.866
> 400000: bitrate 400000 sample-point 0.866
> 500000: bitrate 500000 sample-point 0.866
> 666666: bitrate 666666 sample-point 0.800
> 800000: bitrate 789473 sample-point 0.789 !!!bitrate error 1.3%
> 1000000: bitrate 1000000 sample-point 0.733
>
> With the flexcan serial clock at 40MHz (new value) we get this:
> 5000: no more possible
> 10000: bitrate 10000 sample-point 0.875
> 20000: bitrate 20000 sample-point 0.875
> 40000: bitrate 40000 sample-point 0.850
> 50000: bitrate 50000 sample-point 0.875
> 80000: bitrate 80000 sample-point 0.850
> 100000: bitrate 100000 sample-point 0.875
> 125000: bitrate 125000 sample-point 0.875
> 250000: bitrate 250000 sample-point 0.875
> 400000: bitrate 400000 sample-point 0.850
> 500000: bitrate 500000 sample-point 0.875
> 666666: bitrate 666666 sample-point 0.800
> 800000: bitrate 800000 sample-point 0.800
> 1000000: bitrate 1000000 sample-point 0.750
>
> A drawback of the modification is that 5kbit/s is no more supported.
>
> Setting the flexcan serial clock to 60MHz or 80MHz would produce similar
> results but with losing even more bitrates at the lower end.
>
> Changing the flexcan serial clock to 40MHz might apply for other SoCs
> using the flaxcan module as well (e.g. imx6q/d/s..). But since I don't
> have such hardware to test I did not add this to the patch.
>
> Signed-off-by: Georg Waibel <georg.waibel@wiedemann-group.de>
> ---
> drivers/clk/imx/clk-imx6ul.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
> index dafc8806b03e..5dbb6a937732 100644
> --- a/drivers/clk/imx/clk-imx6ul.c
> +++ b/drivers/clk/imx/clk-imx6ul.c
> @@ -503,7 +503,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
> clk_prepare_enable(hws[IMX6UL_CLK_USBPHY2_GATE]->clk);
> }
>
> - clk_set_parent(hws[IMX6UL_CLK_CAN_SEL]->clk, hws[IMX6UL_CLK_PLL3_60M]->clk);
> + clk_set_parent(hws[IMX6UL_CLK_CAN_SEL]->clk, hws[IMX6UL_CLK_PLL3_80M]->clk);
> if (clk_on_imx6ul())
> clk_set_parent(hws[IMX6UL_CLK_SIM_PRE_SEL]->clk, hws[IMX6UL_CLK_PLL3_USB_OTG]->clk);
> else if (clk_on_imx6ull())
> --
> 2.17.1
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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^ permalink raw reply [flat|nested] 8+ messages in thread* AW: [PATCH] clk: imx: imx6ul: change flexcan clock to support CiA bitrates
2020-03-16 1:30 ` Shawn Guo
@ 2020-03-16 9:55 ` Waibel Georg
2020-03-16 9:58 ` Waibel Georg
0 siblings, 1 reply; 8+ messages in thread
From: Waibel Georg @ 2020-03-16 9:55 UTC (permalink / raw)
To: Shawn Guo
Cc: Stephen Boyd, Michael Turquette, NXP Linux Team, Michel Alex,
Appelt Andreas, Sascha Hauer,
linux-arm-kernel@lists.infradead.org
On Mon, 16 Mar 2020 at 02:30, Shawn Guo <shawnguo@kernel.org> wrote:
> On Wed, Mar 11, 2020 at 12:03:40PM +0000, Waibel Georg wrote:
> > Setting a CAN bitrate of 800kbit/s fails with a bitrate error of 1.3% if the
> > flexcan module is clocked at 30MHz (CAN_CLK_ROOT). This patch changes the clock
> > frequency from 30MHz to 40MHz which allows to support all bitrates recommended
>
> But code changes IMX6UL_CLK_PLL3_60M to IMX6UL_CLK_PLL3_80M? Or
> IMX6UL_CLK_CAN_SEL is different from CAN_CLK_ROOT in the context?
Correct. The patch sets CAN_CLK_SEL to 80MHZ. There is a post-divider
CAN_CLK_PODF which is set to /2 by default which makes the 40MHz
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] clk: imx: imx6ul: change flexcan clock to support CiA bitrates
2020-03-16 9:55 ` AW: " Waibel Georg
@ 2020-03-16 9:58 ` Waibel Georg
2020-03-17 13:48 ` Shawn Guo
0 siblings, 1 reply; 8+ messages in thread
From: Waibel Georg @ 2020-03-16 9:58 UTC (permalink / raw)
To: Shawn Guo
Cc: Stephen Boyd, Michael Turquette, NXP Linux Team, Michel Alex,
Appelt Andreas, Sascha Hauer,
linux-arm-kernel@lists.infradead.org
On Mon, 16 Mar 2020 at 02:30, Shawn Guo <shawnguo@kernel.org> wrote:
> On Wed, Mar 11, 2020 at 12:03:40PM +0000, Waibel Georg wrote:
> > Setting a CAN bitrate of 800kbit/s fails with a bitrate error of 1.3% if the
> > flexcan module is clocked at 30MHz (CAN_CLK_ROOT). This patch changes the clock
> > frequency from 30MHz to 40MHz which allows to support all bitrates recommended
>
> But code changes IMX6UL_CLK_PLL3_60M to IMX6UL_CLK_PLL3_80M? Or
> IMX6UL_CLK_CAN_SEL is different from CAN_CLK_ROOT in the context?
Correct. The patch sets CAN_CLK_SEL to 80MHZ. There is a post-divider
CAN_CLK_PODF which is set to /2 by default which makes the 40MHz
CAN_CLK_ROOT.
Regards
Georg
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] clk: imx: imx6ul: change flexcan clock to support CiA bitrates
2020-03-16 9:58 ` Waibel Georg
@ 2020-03-17 13:48 ` Shawn Guo
2020-03-18 10:33 ` [PATCH V2] " Waibel Georg
0 siblings, 1 reply; 8+ messages in thread
From: Shawn Guo @ 2020-03-17 13:48 UTC (permalink / raw)
To: Waibel Georg
Cc: Stephen Boyd, Michael Turquette, NXP Linux Team, Michel Alex,
Appelt Andreas, Sascha Hauer,
linux-arm-kernel@lists.infradead.org
On Mon, Mar 16, 2020 at 09:58:28AM +0000, Waibel Georg wrote:
> On Mon, 16 Mar 2020 at 02:30, Shawn Guo <shawnguo@kernel.org> wrote:
> > On Wed, Mar 11, 2020 at 12:03:40PM +0000, Waibel Georg wrote:
> > > Setting a CAN bitrate of 800kbit/s fails with a bitrate error of 1.3% if the
> > > flexcan module is clocked at 30MHz (CAN_CLK_ROOT). This patch changes the clock
> > > frequency from 30MHz to 40MHz which allows to support all bitrates recommended
> >
> > But code changes IMX6UL_CLK_PLL3_60M to IMX6UL_CLK_PLL3_80M? Or
> > IMX6UL_CLK_CAN_SEL is different from CAN_CLK_ROOT in the context?
>
> Correct. The patch sets CAN_CLK_SEL to 80MHZ. There is a post-divider
> CAN_CLK_PODF which is set to /2 by default which makes the 40MHz
> CAN_CLK_ROOT.
Could you add this into commit log to make it clear?
Shawn
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH V2] clk: imx: imx6ul: change flexcan clock to support CiA bitrates
2020-03-17 13:48 ` Shawn Guo
@ 2020-03-18 10:33 ` Waibel Georg
2020-04-13 14:22 ` Shawn Guo
0 siblings, 1 reply; 8+ messages in thread
From: Waibel Georg @ 2020-03-18 10:33 UTC (permalink / raw)
To: Shawn Guo
Cc: Stephen Boyd, Michael Turquette, NXP Linux Team, Michel Alex,
Appelt Andreas, Sascha Hauer,
linux-arm-kernel@lists.infradead.org
Setting a CAN bitrate of 800kbit/s fails with a bitrate error of 1.3% if the
flexcan module is clocked at 30MHz (CAN_CLK_ROOT). This patch changes the clock
frequency from 30MHz to 40MHz which allows to support all bitrates recommended
by CiA.
The patch sets CAN_CLK_SEL to 80MHz by changing its clock parent from
CLK_PLL3_60M to CLK_PLL3_80M. The post-divider CAN_CLK_PODF is set to /2 by
default which makes 40MHz CAN_CLK_ROOT from its parent CAN_CLK_SEL.
Background:
CAN in Automation document 102 (CiA102) recommends the CAN bitrates 10, 20, 50,
125, 250, 500, 800 and 1000kbit/s.
With the flexcan serial clock at 30MHz (original value) setting some common
bitrates ("ip link set canX type can bitrate <bitrate>") gives the following
results:
requested value / actually set value
5000: bitrate 5000 sample-point 0.708
10000: bitrate 10000 sample-point 0.866
20000: bitrate 20000 sample-point 0.866
40000: bitrate 40000 sample-point 0.866
50000: bitrate 50000 sample-point 0.866
80000: bitrate 80000 sample-point 0.866
100000: bitrate 100000 sample-point 0.866
125000: bitrate 125000 sample-point 0.875
250000: bitrate 250000 sample-point 0.866
400000: bitrate 400000 sample-point 0.866
500000: bitrate 500000 sample-point 0.866
666666: bitrate 666666 sample-point 0.800
800000: bitrate 789473 sample-point 0.789 !!!bitrate error 1.3%
1000000: bitrate 1000000 sample-point 0.733
With the flexcan serial clock at 40MHz (new value) we get this:
5000: no more possible
10000: bitrate 10000 sample-point 0.875
20000: bitrate 20000 sample-point 0.875
40000: bitrate 40000 sample-point 0.850
50000: bitrate 50000 sample-point 0.875
80000: bitrate 80000 sample-point 0.850
100000: bitrate 100000 sample-point 0.875
125000: bitrate 125000 sample-point 0.875
250000: bitrate 250000 sample-point 0.875
400000: bitrate 400000 sample-point 0.850
500000: bitrate 500000 sample-point 0.875
666666: bitrate 666666 sample-point 0.800
800000: bitrate 800000 sample-point 0.800
1000000: bitrate 1000000 sample-point 0.750
A drawback of the modification is that 5kbit/s is no more supported.
Setting the flexcan serial clock to 60MHz or 80MHz would produce similar
results but with losing even more bitrates at the lower end.
Changing the flexcan serial clock to 40MHz might apply for other SoCs
using the flaxcan module as well (e.g. imx6q/d/s..). But since I don't
have such hardware to test I did not add this to the patch.
Signed-off-by: Georg Waibel <georg.waibel@wiedemann-group.de>
---
V2: Added some technical details to commit log.
---
drivers/clk/imx/clk-imx6ul.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index dafc8806b03e..5dbb6a937732 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -503,7 +503,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
clk_prepare_enable(hws[IMX6UL_CLK_USBPHY2_GATE]->clk);
}
- clk_set_parent(hws[IMX6UL_CLK_CAN_SEL]->clk, hws[IMX6UL_CLK_PLL3_60M]->clk);
+ clk_set_parent(hws[IMX6UL_CLK_CAN_SEL]->clk, hws[IMX6UL_CLK_PLL3_80M]->clk);
if (clk_on_imx6ul())
clk_set_parent(hws[IMX6UL_CLK_SIM_PRE_SEL]->clk, hws[IMX6UL_CLK_PLL3_USB_OTG]->clk);
else if (clk_on_imx6ull())
--
2.17.1
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^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH V2] clk: imx: imx6ul: change flexcan clock to support CiA bitrates
2020-03-18 10:33 ` [PATCH V2] " Waibel Georg
@ 2020-04-13 14:22 ` Shawn Guo
2024-06-28 8:08 ` Random flexcan probe error on i.MX6ULL after flexcan clock increase Enguerrand de Ribaucourt
0 siblings, 1 reply; 8+ messages in thread
From: Shawn Guo @ 2020-04-13 14:22 UTC (permalink / raw)
To: Waibel Georg
Cc: Stephen Boyd, Michael Turquette, NXP Linux Team, Michel Alex,
Appelt Andreas, Sascha Hauer,
linux-arm-kernel@lists.infradead.org
On Wed, Mar 18, 2020 at 10:33:24AM +0000, Waibel Georg wrote:
> Setting a CAN bitrate of 800kbit/s fails with a bitrate error of 1.3% if the
> flexcan module is clocked at 30MHz (CAN_CLK_ROOT). This patch changes the clock
> frequency from 30MHz to 40MHz which allows to support all bitrates recommended
> by CiA.
>
> The patch sets CAN_CLK_SEL to 80MHz by changing its clock parent from
> CLK_PLL3_60M to CLK_PLL3_80M. The post-divider CAN_CLK_PODF is set to /2 by
> default which makes 40MHz CAN_CLK_ROOT from its parent CAN_CLK_SEL.
>
> Background:
> CAN in Automation document 102 (CiA102) recommends the CAN bitrates 10, 20, 50,
> 125, 250, 500, 800 and 1000kbit/s.
>
> With the flexcan serial clock at 30MHz (original value) setting some common
> bitrates ("ip link set canX type can bitrate <bitrate>") gives the following
> results:
> requested value / actually set value
> 5000: bitrate 5000 sample-point 0.708
> 10000: bitrate 10000 sample-point 0.866
> 20000: bitrate 20000 sample-point 0.866
> 40000: bitrate 40000 sample-point 0.866
> 50000: bitrate 50000 sample-point 0.866
> 80000: bitrate 80000 sample-point 0.866
> 100000: bitrate 100000 sample-point 0.866
> 125000: bitrate 125000 sample-point 0.875
> 250000: bitrate 250000 sample-point 0.866
> 400000: bitrate 400000 sample-point 0.866
> 500000: bitrate 500000 sample-point 0.866
> 666666: bitrate 666666 sample-point 0.800
> 800000: bitrate 789473 sample-point 0.789 !!!bitrate error 1.3%
> 1000000: bitrate 1000000 sample-point 0.733
>
> With the flexcan serial clock at 40MHz (new value) we get this:
> 5000: no more possible
> 10000: bitrate 10000 sample-point 0.875
> 20000: bitrate 20000 sample-point 0.875
> 40000: bitrate 40000 sample-point 0.850
> 50000: bitrate 50000 sample-point 0.875
> 80000: bitrate 80000 sample-point 0.850
> 100000: bitrate 100000 sample-point 0.875
> 125000: bitrate 125000 sample-point 0.875
> 250000: bitrate 250000 sample-point 0.875
> 400000: bitrate 400000 sample-point 0.850
> 500000: bitrate 500000 sample-point 0.875
> 666666: bitrate 666666 sample-point 0.800
> 800000: bitrate 800000 sample-point 0.800
> 1000000: bitrate 1000000 sample-point 0.750
>
> A drawback of the modification is that 5kbit/s is no more supported.
>
> Setting the flexcan serial clock to 60MHz or 80MHz would produce similar
> results but with losing even more bitrates at the lower end.
>
> Changing the flexcan serial clock to 40MHz might apply for other SoCs
> using the flaxcan module as well (e.g. imx6q/d/s..). But since I don't
> have such hardware to test I did not add this to the patch.
>
> Signed-off-by: Georg Waibel <georg.waibel@wiedemann-group.de>
Applied, thanks.
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^ permalink raw reply [flat|nested] 8+ messages in thread* Random flexcan probe error on i.MX6ULL after flexcan clock increase
2020-04-13 14:22 ` Shawn Guo
@ 2024-06-28 8:08 ` Enguerrand de Ribaucourt
0 siblings, 0 replies; 8+ messages in thread
From: Enguerrand de Ribaucourt @ 2024-06-28 8:08 UTC (permalink / raw)
To: shawnguo
Cc: Alex.Michel, Andreas.Appelt, Georg.Waibel, linux-arm-kernel,
linux-imx, mturquette, s.hauer, sboyd
Hello,
This patch which increased the flexcan clock on i.MX6UL to support higher
bitrates introduced a regression on i.MX6ULL. On my range of devices, on
software reboot (reboot command), the flexcan driver would randomly fail to
probe with the following error:
[ 1.215064] CAN device driver interface
[ 1.217467] flexcan 2090000.can: registering netdev failed
[ 1.217515] flexcan: probe of 2090000.can failed with error -110
After investigating, the function flexcan_chip_disable() in
register_flexcandev() fails to get the low power mode acknowledgement bit from
the flexcan module. Forcing a probe again, or even toggling the soft reset bit
afterwards does not help. Only another software reboot will unblock the module.
This error hapens on all my devices roughly 0.1% of reboots. It is the only
random error I have seen on my board so far while none existed when I was using
a 5.4 kernel.
The i.MX6ULL reference manual states that the maximum frequency for the flexcan
is 80MHz, which is the same for the i.MX6UL. This commit's message states that
it increased the frequency from 30MHz to 40MHz with the divider, however it's
using a 80MHz clock source. I'm wondering if the clock source is too fast?
Reverting this commit fixed the issue. I'd like to ask the maintainers if we
should revert it or if another solution can be found to both satisfy the higher
bitrate and not have the reboot issue.
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2024-06-28 8:09 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-03-11 12:03 [PATCH] clk: imx: imx6ul: change flexcan clock to support CiA bitrates Waibel Georg
2020-03-16 1:30 ` Shawn Guo
2020-03-16 9:55 ` AW: " Waibel Georg
2020-03-16 9:58 ` Waibel Georg
2020-03-17 13:48 ` Shawn Guo
2020-03-18 10:33 ` [PATCH V2] " Waibel Georg
2020-04-13 14:22 ` Shawn Guo
2024-06-28 8:08 ` Random flexcan probe error on i.MX6ULL after flexcan clock increase Enguerrand de Ribaucourt
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