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Sat, 28 Mar 2020 08:32:24 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 710F3C433BA; Sat, 28 Mar 2020 08:32:24 +0000 (UTC) Received: from ecbld-sh028-lnx.qualcomm.com (unknown [180.166.53.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: tingwei) by smtp.codeaurora.org (Postfix) with ESMTPSA id 53950C433F2; Sat, 28 Mar 2020 08:32:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 53950C433F2 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=tingwei@codeaurora.org From: Tingwei Zhang To: Will Deacon , Mark Rutland Subject: [PATCH] arm64: hw_breakpoint: don't clear debug registers in halt mode Date: Sat, 28 Mar 2020 16:32:09 +0800 Message-Id: <20200328083209.21793-1-tingwei@codeaurora.org> X-Mailer: git-send-email 2.20.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200328_013235_668031_33F32661 X-CRM114-Status: GOOD ( 13.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Catalin Marinas , linux-arm-kernel@lists.infradead.org, Tingwei Zhang , linux-kernel@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org If external debugger sets a breakpoint for one Kernel function when device is in bootloader mode and loads Kernel, this breakpoint will be wiped out in hw_breakpoint_reset(). To fix this, check MDSCR_EL1.HDE in hw_breakpoint_reset(). When MDSCR_EL1.HDE is 0b1, halting debug is enabled. Don't reset debug registers in this case. Signed-off-by: Tingwei Zhang --- arch/arm64/include/asm/debug-monitors.h | 1 + arch/arm64/kernel/hw_breakpoint.c | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/arch/arm64/include/asm/debug-monitors.h b/arch/arm64/include/asm/debug-monitors.h index 7619f473155f..8dc2c28791a0 100644 --- a/arch/arm64/include/asm/debug-monitors.h +++ b/arch/arm64/include/asm/debug-monitors.h @@ -18,6 +18,7 @@ /* MDSCR_EL1 enabling bits */ #define DBG_MDSCR_KDE (1 << 13) +#define DBG_MDSCR_HDE (1 << 14) #define DBG_MDSCR_MDE (1 << 15) #define DBG_MDSCR_MASK ~(DBG_MDSCR_KDE | DBG_MDSCR_MDE) diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_breakpoint.c index 0b727edf4104..0180306f74d7 100644 --- a/arch/arm64/kernel/hw_breakpoint.c +++ b/arch/arm64/kernel/hw_breakpoint.c @@ -927,6 +927,17 @@ void hw_breakpoint_thread_switch(struct task_struct *next) !next_debug_info->wps_disabled); } +/* + * Check if halted debug mode is enabled. + */ +static u32 hde_enabled(void) +{ + u32 mdscr; + + asm volatile("mrs %0, mdscr_el1" : "=r" (mdscr)); + return (mdscr & DBG_MDSCR_HDE); +} + /* * CPU initialisation. */ @@ -934,6 +945,14 @@ static int hw_breakpoint_reset(unsigned int cpu) { int i; struct perf_event **slots; + + /* + * When halting debug mode is enabled, break point could be already + * set be external debugger. Don't reset debug registers here to + * reserve break point from external debugger. + */ + if (hde_enabled()) + return 0; /* * When a CPU goes through cold-boot, it does not have any installed * slot, so it is safe to share the same function for restoring and -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel