From: Qiang Yu <yuq825@gmail.com>
To: devicetree@vger.kernel.org, linux-sunxi@googlegroups.com
Cc: Mark Rutland <mark.rutland@arm.com>,
lima@lists.freedesktop.org, Maxime Ripard <mripard@kernel.org>,
Chen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>,
Qiang Yu <yuq825@gmail.com>,
linux-arm-kernel@lists.infradead.org,
Icenowy Zheng <icenowy@aosc.io>
Subject: [PATCH] ARM: dts: sun8i-h3: add opp table for mali gpu
Date: Sat, 28 Mar 2020 17:16:32 +0800 [thread overview]
Message-ID: <20200328091632.12837-1-yuq825@gmail.com> (raw)
OPP table vaule is get from orangepi lichee linux-3.4
kernel driver.
Signed-off-by: Qiang Yu <yuq825@gmail.com>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 20217e2ca4d3..53ef9a18e953 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -128,6 +128,23 @@
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
+ gpu_opp_table: gpu-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-120000000 {
+ opp-hz = /bits/ 64 <120000000>;
+ };
+ opp-312000000 {
+ opp-hz = /bits/ 64 <312000000>;
+ };
+ opp-432000000 {
+ opp-hz = /bits/ 64 <432000000>;
+ };
+ opp-576000000 {
+ opp-hz = /bits/ 64 <576000000>;
+ };
+ };
+
soc {
deinterlace: deinterlace@1400000 {
compatible = "allwinner,sun8i-h3-deinterlace";
@@ -205,8 +222,7 @@
clock-names = "bus", "core";
resets = <&ccu RST_BUS_GPU>;
- assigned-clocks = <&ccu CLK_GPU>;
- assigned-clock-rates = <384000000>;
+ operating-points-v2 = <&gpu_opp_table>;
};
ths: thermal-sensor@1c25000 {
--
2.17.1
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next reply other threads:[~2020-03-28 9:17 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-28 9:16 Qiang Yu [this message]
2020-03-30 17:53 ` [PATCH] ARM: dts: sun8i-h3: add opp table for mali gpu Maxime Ripard
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