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Wed, 01 Apr 2020 11:28:03 +0100 Date: Wed, 1 Apr 2020 11:27:57 +0100 From: Marc Zyngier To: Zenghui Yu Subject: Re: [PATCH] KVM: arm64: vgic-v3: Clear pending bit in guest memory after synchronization Message-ID: <20200401112757.6716cbf3@why> In-Reply-To: References: <20200331031245.1562-1-yuzenghui@huawei.com> <20200331090709.17d2087d@why> Organization: Approximate X-Mailer: Claws Mail 3.17.5 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: yuzenghui@huawei.com, kvmarm@lists.cs.columbia.edu, eric.auger@redhat.com, andre.przywara@arm.com, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, wanghaibin.wang@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200401_032806_304800_00E2840E X-CRM114-Status: GOOD ( 20.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: suzuki.poulose@arm.com, andre.przywara@arm.com, linux-kernel@vger.kernel.org, eric.auger@redhat.com, james.morse@arm.com, linux-arm-kernel@lists.infradead.org, wanghaibin.wang@huawei.com, kvmarm@lists.cs.columbia.edu, julien.thierry.kdev@gmail.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 31 Mar 2020 17:11:37 +0800 Zenghui Yu wrote: Hi Zenghui, > Hi Marc, > > On 2020/3/31 16:07, Marc Zyngier wrote: > > Hi Zenghui, [...] > >> > > I've been thinking about this, and I wonder why we don't simply clear > > the whole pending table instead of carefully wiping it one bit at a > > time. My reasoning is that if a LPI isn't mapped, then it cannot be made > > pending the first place. > > A writing to GICR_CTLR.EnableLPIs can happen in parallel with MAPTI/INT > command sequence, where the new LPI is mapped to *this* vcpu and made > pending, wrong? I think commit 7d8b44c54e0c had described it in detail. I'm not sure this commit is relevant here. It describes how the configuration is picked up by MAPTI, not how the pending bit got there the first place. > But thinking that we cache the pending bit in pending_latch (instead of > writing the corresponding bit in guest memory) when a LPI is made > pending, it seems to be safe to clear the whole pending table here. Yes, and this is my worry. The spec is pretty vague about what the behaviour of the redistributor is when something is set in the pending table. At the moment, we treat these bits as if they had been generated by a translation, but we do so inconsistently: we only pick these bits up and generate a LPI if there is a mapping at the ITS level. If these bits are relevant, we should forward a LPI to the CPU. It feels we're in UNPREDICTIBLE land... > > > > > And I think there is a similar issue in vgic_v3_lpi_sync_pending_status(). > > Why sync something back from the pending table when the LPI wasn't > > mapped yet? > > vgic_v3_lpi_sync_pending_status() can be called on the ITE restore path: > vgic_its_restore_ite/vgic_add_lpi/vgic_v3_lpi_sync_pending_status. > We should rely on it to sync the pending bit from guest memory (which > was saved on the source side). The fact that we have *two* paths to restore pending bits is pretty annoying. There is certainly some scope for simplification here. Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel