[PATCH 0/7] Add support for Allwinner H6 DVFS

[PATCH 0/7] Add support for Allwinner H6 DVFS

[Clément Péron]

Hi Sunxi maintainers and members,

Now that required drivers are merged we can contibute on DVFS support for
Allwinner H6.

This serie is based on Yangtao Li serie[0] and Megous works[1].

Most of the OPP tables are taken from original vendor kernel[2].
Plus there is a new CPU frequency @1.8GHz.

I wrote a simple script to randomly set a frequency during a random time[3].
With this script and using stress-ng during a day I didn't see any issue.
Moreover I have tested specifically the 1.8GHz on my Beelink GS1, max thermal
80°C is reached after ~10min and then the SoC oscillates quickly between 1.5
and 1.8GHz.

I also test that that offlining CPU0 and doing DVFS on other CPUs works.
As CPU regulator is only set for CPU0.

But maybe it doesn't cost much to set the regulator for all the CPUs?

Jernej test the GPU devfreq on several H6 board particulary the Tanix TX6 which
doesn't have a proper dedicated PMIC and doesn't had any trouble with it.

Do you think I can enable GPU OPP for all H6 Boards?

Also Yangtao Li enable DVFS for OrangePi and Pine64, as I can't test them I
didn't reenable these boards. Please, let me know if you want me to add these
boards in this serie.

Thanks,
Clément

0: https://patchwork.kernel.org/cover/10815117/
1: https://megous.com/git/linux/log/?h=ths-5.7
2: https://github.com/orangepi-xunlong/OrangePiH6_Linux4_9/blob/master/arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi#L345-L517
3: https://gist.github.com/clementperon/55a055dae3f13bbd14fb39c0069fe2e2

Clément Péron (4):
  arm64: dts: allwinner: h6: set thermal polling time
  arm64: dts: allwinner: h6: Add GPU Operating Performance Points table
  arm64: configs: Enable sun50i cpufreq nvmem
  arm64: dts: allwinner: h6: Enable CPU and GPU opp tables for Beelink
    GS1

Ondrej Jirman (2):
  arm64: dts: allwinner: h6: Add thermal trip points/cooling map
  arm64: dts: allwinner: h6: Add CPU Operating Performance Points table

Yangtao Li (1):
  arm64: dts: allwinner: h6: Add clock to CPU cores

 .../dts/allwinner/sun50i-h6-beelink-gs1.dts   |  10 +-
 .../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 103 ++++++++++++++++++
 .../boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi |  74 +++++++++++++
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  |  44 +++++++-
 arch/arm64/configs/defconfig                  |   1 +
 5 files changed, 226 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
 create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi

-- 
2.20.1


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[PATCH 1/7] arm64: dts: allwinner: h6: Add clock to CPU cores

[Clément Péron]

From: Yangtao Li <tiny.windzz@gmail.com>

The ARM CPU cores are fed by the CPU clock from the CCU. Add a
reference to the clock for each CPU core, along with the clock
transition latency.

Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 3329283e38ab..aef4ae760d5e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -25,6 +25,8 @@
 			device_type = "cpu";
 			reg = <0>;
 			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
 		};
 
 		cpu1: cpu@1 {
@@ -32,6 +34,8 @@
 			device_type = "cpu";
 			reg = <1>;
 			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
 		};
 
 		cpu2: cpu@2 {
@@ -39,6 +43,8 @@
 			device_type = "cpu";
 			reg = <2>;
 			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
 		};
 
 		cpu3: cpu@3 {
@@ -46,6 +52,8 @@
 			device_type = "cpu";
 			reg = <3>;
 			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
 		};
 	};
 
-- 
2.20.1


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[PATCH 2/7] arm64: dts: allwinner: h6: Add thermal trip points/cooling map

[Clément Péron]

From: Ondrej Jirman <megous@megous.com>

This enables passive cooling by down-regulating CPU voltage
and frequency.

Signed-off-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 24 ++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index aef4ae760d5e..d4d3963705f5 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -908,6 +908,30 @@
 			polling-delay-passive = <0>;
 			polling-delay = <0>;
 			thermal-sensors = <&ths 0>;
+
+			trips {
+				cpu_hot_trip: cpu-hot {
+					temperature = <80000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu_very_hot_trip: cpu-very-hot {
+					temperature = <100000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				cpu-hot-limit {
+					trip = <&cpu_hot_trip>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 
 		gpu-thermal {
-- 
2.20.1


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[PATCH 3/7] arm64: dts: allwinner: h6: set thermal polling time

[Clément Péron]

Add reasonable thermal polling time for Allwinner H6.

Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index d4d3963705f5..c3e4f09f60ce 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -905,8 +905,8 @@
 
 	thermal-zones {
 		cpu-thermal {
-			polling-delay-passive = <0>;
-			polling-delay = <0>;
+			polling-delay-passive = <100>;
+			polling-delay = <1000>;
 			thermal-sensors = <&ths 0>;
 
 			trips {
@@ -935,8 +935,8 @@
 		};
 
 		gpu-thermal {
-			polling-delay-passive = <0>;
-			polling-delay = <0>;
+			polling-delay-passive = <100>;
+			polling-delay = <1000>;
 			thermal-sensors = <&ths 1>;
 		};
 	};
-- 
2.20.1


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Re: [linux-sunxi] [PATCH 3/7] arm64: dts: allwinner: h6: set thermal polling time

[Ondřej Jirman]

Hello,

On Sun, Apr 05, 2020 at 12:49:09PM +0200, Clément Péron wrote:
> Add reasonable thermal polling time for Allwinner H6.
> 
> Signed-off-by: Clément Péron <peron.clem@gmail.com>
> ---
>  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> index d4d3963705f5..c3e4f09f60ce 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> @@ -905,8 +905,8 @@
>  
>  	thermal-zones {
>  		cpu-thermal {
> -			polling-delay-passive = <0>;
> -			polling-delay = <0>;
> +			polling-delay-passive = <100>;
> +			polling-delay = <1000>;
>  			thermal-sensors = <&ths 0>;

This is not necessary, and will not do anything useful, since the driver
uses interrupts to update the thermal zone's temperature. Please keep the
values at 0.

With your settings the thermal zone would just add a polling timer in addition
to being updated every 250ms via THS interrupt. The real thermal measurements
are available every 250ms anyway, so setting a smaller period here will not do
anything useful, and 1s period will not lead to slower updates either.

Values of 0 mean tell the thermal zone to rely on thermal driver to update
the thermal zone by itself (via interrupt) and to not poll.

regards,
	o.

>  			trips {
> @@ -935,8 +935,8 @@
>  		};
>  
>  		gpu-thermal {
> -			polling-delay-passive = <0>;
> -			polling-delay = <0>;
> +			polling-delay-passive = <100>;
> +			polling-delay = <1000>;
>  			thermal-sensors = <&ths 1>;
>  		};
>  	};
> -- 
> 2.20.1
> 
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Re: [linux-sunxi] [PATCH 3/7] arm64: dts: allwinner: h6: set thermal polling time

[Clément Péron]

Hi Ondřej,

On Sun, 5 Apr 2020 at 13:24, Ondřej Jirman <megous@megous.com> wrote:
>
> Hello,
>
> On Sun, Apr 05, 2020 at 12:49:09PM +0200, Clément Péron wrote:
> > Add reasonable thermal polling time for Allwinner H6.
> >
> > Signed-off-by: Clément Péron <peron.clem@gmail.com>
> > ---
> >  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 8 ++++----
> >  1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > index d4d3963705f5..c3e4f09f60ce 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > @@ -905,8 +905,8 @@
> >
> >       thermal-zones {
> >               cpu-thermal {
> > -                     polling-delay-passive = <0>;
> > -                     polling-delay = <0>;
> > +                     polling-delay-passive = <100>;
> > +                     polling-delay = <1000>;
> >                       thermal-sensors = <&ths 0>;
>
> This is not necessary, and will not do anything useful, since the driver
> uses interrupts to update the thermal zone's temperature. Please keep the
> values at 0.
>
> With your settings the thermal zone would just add a polling timer in addition
> to being updated every 250ms via THS interrupt. The real thermal measurements
> are available every 250ms anyway, so setting a smaller period here will not do
> anything useful, and 1s period will not lead to slower updates either.
>
> Values of 0 mean tell the thermal zone to rely on thermal driver to update
> the thermal zone by itself (via interrupt) and to not poll.

Thanks for the explanations,
I will drop this patch.

Regards,
Clément
>
> regards,
>         o.
>
> >                       trips {
> > @@ -935,8 +935,8 @@
> >               };
> >
> >               gpu-thermal {
> > -                     polling-delay-passive = <0>;
> > -                     polling-delay = <0>;
> > +                     polling-delay-passive = <100>;
> > +                     polling-delay = <1000>;
> >                       thermal-sensors = <&ths 1>;
> >               };
> >       };
> > --
> > 2.20.1
> >
> > --
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[PATCH 4/7] arm64: dts: allwinner: h6: Add CPU Operating Performance Points table

[Clément Péron]

From: Ondrej Jirman <megous@megous.com>

Add an Operating Performance Points table for the CPU cores to
enable Dynamic Voltage & Frequency Scaling on the H6.

Signed-off-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
 .../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 103 ++++++++++++++++++
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  |   4 +
 2 files changed, 107 insertions(+)
 create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
new file mode 100644
index 000000000000..b480c33f426b
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
+// Copyright (C) 2020 Clément Péron <peron.clem@gmail.com>
+
+/ {
+	cpu0_opp_table: opp_table0 {
+		compatible = "allwinner,sun50i-h6-operating-points";
+		nvmem-cells = <&speedbin_efuse>;
+		opp-shared;
+
+		opp@480000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <480000000>;
+
+			opp-microvolt-speed0 = <880000>;
+			opp-microvolt-speed1 = <820000>;
+			opp-microvolt-speed2 = <820000>;
+		};
+
+		opp@720000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <720000000>;
+
+			opp-microvolt-speed0 = <880000>;
+			opp-microvolt-speed1 = <820000>;
+			opp-microvolt-speed2 = <820000>;
+		};
+
+		opp@816000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <816000000>;
+
+			opp-microvolt-speed0 = <880000>;
+			opp-microvolt-speed1 = <820000>;
+			opp-microvolt-speed2 = <820000>;
+		};
+
+		opp@888000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <888000000>;
+
+			opp-microvolt-speed0 = <880000>;
+			opp-microvolt-speed1 = <820000>;
+			opp-microvolt-speed2 = <820000>;
+		};
+
+		opp@1080000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <1080000000>;
+
+			opp-microvolt-speed0 = <940000>;
+			opp-microvolt-speed1 = <880000>;
+			opp-microvolt-speed2 = <880000>;
+		};
+
+		opp@1320000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <1320000000>;
+
+			opp-microvolt-speed0 = <1000000>;
+			opp-microvolt-speed1 = <940000>;
+			opp-microvolt-speed2 = <940000>;
+		};
+
+		opp@1488000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <1488000000>;
+
+			opp-microvolt-speed0 = <1060000>;
+			opp-microvolt-speed1 = <1000000>;
+			opp-microvolt-speed2 = <1000000>;
+		};
+
+		opp@1800000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <1800000000>;
+
+			opp-microvolt-speed0 = <1160000>;
+			opp-microvolt-speed1 = <1100000>;
+			opp-microvolt-speed2 = <1100000>;
+		};
+	};
+};
+
+&cpu0 {
+	operating-points-v2 = <&cpu0_opp_table>;
+	#cooling-cells = <2>;
+};
+
+&cpu1 {
+	operating-points-v2 = <&cpu0_opp_table>;
+	#cooling-cells = <2>;
+};
+
+&cpu2 {
+	operating-points-v2 = <&cpu0_opp_table>;
+	#cooling-cells = <2>;
+};
+
+&cpu3 {
+	operating-points-v2 = <&cpu0_opp_table>;
+	#cooling-cells = <2>;
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index c3e4f09f60ce..a9304fec245c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -253,6 +253,10 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
+			speedbin_efuse: speed@1c {
+				reg = <0x1c 0x4>;
+			};
+
 			ths_calibration: thermal-sensor-calibration@14 {
 				reg = <0x14 0x8>;
 			};
-- 
2.20.1


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[PATCH 5/7] arm64: dts: allwinner: h6: Add GPU Operating Performance Points table

[Clément Péron]

Add an Operating Performance Points table for the GPU to
enable Dynamic Voltage & Frequency Scaling on the H6.

Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
 .../boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi | 74 +++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi
new file mode 100644
index 000000000000..4a1814844fe0
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Clément Péron <peron.clem@gmail.com>
+
+/ {
+	gpu_opp_table: opp_table1 {
+		compatible = "operating-points-v2";
+
+		opp@756000000 {
+			opp-hz = /bits/ 64 <756000000>;
+			opp-microvolt = <1040000>;
+		};
+		opp@624000000 {
+			opp-hz = /bits/ 64 <624000000>;
+			opp-microvolt = <950000>;
+		};
+		opp@576000000 {
+			opp-hz = /bits/ 64 <576000000>;
+			opp-microvolt = <930000>;
+		};
+		opp@540000000 {
+			opp-hz = /bits/ 64 <540000000>;
+			opp-microvolt = <910000>;
+		};
+		opp@504000000 {
+			opp-hz = /bits/ 64 <504000000>;
+			opp-microvolt = <890000>;
+		};
+		opp@456000000 {
+			opp-hz = /bits/ 64 <456000000>;
+			opp-microvolt = <870000>;
+		};
+		opp@432000000 {
+			opp-hz = /bits/ 64 <432000000>;
+			opp-microvolt = <860000>;
+		};
+		opp@420000000 {
+			opp-hz = /bits/ 64 <420000000>;
+			opp-microvolt = <850000>;
+		};
+		opp@408000000 {
+			opp-hz = /bits/ 64 <408000000>;
+			opp-microvolt = <840000>;
+		};
+		opp@384000000 {
+			opp-hz = /bits/ 64 <384000000>;
+			opp-microvolt = <830000>;
+		};
+		opp@360000000 {
+			opp-hz = /bits/ 64 <360000000>;
+			opp-microvolt = <820000>;
+		};
+		opp@336000000 {
+			opp-hz = /bits/ 64 <336000000>;
+			opp-microvolt = <810000>;
+		};
+		opp@312000000 {
+			opp-hz = /bits/ 64 <312000000>;
+			opp-microvolt = <810000>;
+		};
+		opp@264000000 {
+			opp-hz = /bits/ 64 <264000000>;
+			opp-microvolt = <810000>;
+		};
+		opp@216000000 {
+			opp-hz = /bits/ 64 <216000000>;
+			opp-microvolt = <810000>;
+		};
+	};
+};
+
+&gpu {
+	operating-points-v2 = <&gpu_opp_table>;
+	#cooling-cells = <2>;
+};
-- 
2.20.1


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[PATCH 6/7] arm64: configs: Enable sun50i cpufreq nvmem

[Clément Péron]

Allwinner H6 needs this driver to be able to get
the correct speed_bin required for DVFS.

Enable this option in arm64 defconfig.

Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 4db223dbc549..28b25fc0347c 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -83,6 +83,7 @@ CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
 CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
 CONFIG_CPUFREQ_DT=y
 CONFIG_ACPI_CPPC_CPUFREQ=m
+CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
 CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
 CONFIG_ARM_SCPI_CPUFREQ=y
 CONFIG_ARM_IMX_CPUFREQ_DT=m
-- 
2.20.1


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[PATCH 7/7] arm64: dts: allwinner: h6: Enable CPU and GPU opp tables for Beelink GS1

[Clément Péron]

Enable CPU and GPU opp tables for Beelink GS1.

This needs also to change the CPU regulator min/max voltage to fit
the OPP table.

Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
 .../arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index df6d872c34e2..8e65d56a7c85 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
@@ -4,6 +4,8 @@
 /dts-v1/;
 
 #include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"
+#include "sun50i-h6-gpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
@@ -70,6 +72,10 @@
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&reg_dcdca>;
+};
+
 &de {
 	status = "okay";
 };
@@ -226,8 +232,8 @@
 
 			reg_dcdca: dcdca {
 				regulator-always-on;
-				regulator-min-microvolt = <810000>;
-				regulator-max-microvolt = <1080000>;
+				regulator-min-microvolt = <820000>;
+				regulator-max-microvolt = <1160000>;
 				regulator-name = "vdd-cpu";
 			};
 
-- 
2.20.1


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Re: [linux-sunxi] [PATCH 7/7] arm64: dts: allwinner: h6: Enable CPU and GPU opp tables for Beelink GS1

[Ondřej Jirman]

Hello,

On Sun, Apr 05, 2020 at 12:49:13PM +0200, Clément Péron wrote:
> Enable CPU and GPU opp tables for Beelink GS1.
> 
> This needs also to change the CPU regulator min/max voltage to fit
> the OPP table.
> 
> Signed-off-by: Clément Péron <peron.clem@gmail.com>
> ---
>  .../arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> index df6d872c34e2..8e65d56a7c85 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
> @@ -4,6 +4,8 @@
>  /dts-v1/;
>  
>  #include "sun50i-h6.dtsi"
> +#include "sun50i-h6-cpu-opp.dtsi"
> +#include "sun50i-h6-gpu-opp.dtsi"
>  
>  #include <dt-bindings/gpio/gpio.h>
>  
> @@ -70,6 +72,10 @@
>  	};
>  };
>  
> +&cpu0 {
> +	cpu-supply = <&reg_dcdca>;
> +};
> +
>  &de {
>  	status = "okay";
>  };
> @@ -226,8 +232,8 @@
>  
>  			reg_dcdca: dcdca {
>  				regulator-always-on;
> -				regulator-min-microvolt = <810000>;
> -				regulator-max-microvolt = <1080000>;
> +				regulator-min-microvolt = <820000>;
> +				regulator-max-microvolt = <1160000>;

The H6 datasheet says:

- VDD-CPU Power Supply for CPU  0.81 - 1.08 V (recommended)
- VDD-CPU Power Supply for CPU -0.30 - 1.30 V (abs max)

So I guess there's no need to increase the lower limit, because it matches
the datasheet already.

regards,
	o.

>  				regulator-name = "vdd-cpu";
>  			};
>  
> -- 
> 2.20.1
> 
> -- 
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Re: [linux-sunxi] [PATCH 0/7] Add support for Allwinner H6 DVFS

[Ondřej Jirman]

Hello Clément,

On Sun, Apr 05, 2020 at 12:49:06PM +0200, Clément Péron wrote:
> Hi Sunxi maintainers and members,
> 
> Now that required drivers are merged we can contibute on DVFS support for
> Allwinner H6.
> 
> This serie is based on Yangtao Li serie[0] and Megous works[1].
> 
> Most of the OPP tables are taken from original vendor kernel[2].
> Plus there is a new CPU frequency @1.8GHz.
> 
> I wrote a simple script to randomly set a frequency during a random time[3].
> With this script and using stress-ng during a day I didn't see any issue.
> Moreover I have tested specifically the 1.8GHz on my Beelink GS1, max thermal
> 80°C is reached after ~10min and then the SoC oscillates quickly between 1.5
> and 1.8GHz.

Thank you for working on this. :) I wonder what SoC bin you tested this on.

I have a patch to print it here:

  https://megous.com/git/linux/commit/?h=ths-5.7&id=c5ddd2a45c7e04dcec31619b58de7c798ad6594c

> I also test that that offlining CPU0 and doing DVFS on other CPUs works.
> As CPU regulator is only set for CPU0.
> 
> But maybe it doesn't cost much to set the regulator for all the CPUs?
> 
> Jernej test the GPU devfreq on several H6 board particulary the Tanix TX6 which
> doesn't have a proper dedicated PMIC and doesn't had any trouble with it.
> 
> Do you think I can enable GPU OPP for all H6 Boards?
> 
> Also Yangtao Li enable DVFS for OrangePi and Pine64, as I can't test them I
> didn't reenable these boards. Please, let me know if you want me to add these
> boards in this serie.

Feel free to add these OPPs also to OrangePi 3 dts, I've been running mine with
this OPP table for at least a year already (I have the worst SoC bin).

Though I'll run a bit more comprehensive test for more frequencies, like you
did, just to be sure.

One thing I wonder about is if there should not be some small ramp delay on the
CPU regulator node, because voltage change probably takes some small time to
apply, compared to changing the PLL frequency. And I have no idea if the CPU
is not running for some very small time out of spec during transitions.

I didn't find timing information in the PMIC datasheet, but I suppose based
on the DCDCA frequency of 3MHz that it will adapt to the new voltage in the
range of 1s-10s of microseconds.

In datasheet of the similar PMIC (AXP813) there is this note:

  DVM (Dynamic Voltage scaling Management) ramp rate: 2.5mV/us at buck frequency 3MHz

I think it will be simiar with AXP805.

regards,
	o.

> Thanks,
> Clément
> 
> 0: https://patchwork.kernel.org/cover/10815117/
> 1: https://megous.com/git/linux/log/?h=ths-5.7
> 2: https://github.com/orangepi-xunlong/OrangePiH6_Linux4_9/blob/master/arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi#L345-L517
> 3: https://gist.github.com/clementperon/55a055dae3f13bbd14fb39c0069fe2e2
> 
> Clément Péron (4):
>   arm64: dts: allwinner: h6: set thermal polling time
>   arm64: dts: allwinner: h6: Add GPU Operating Performance Points table
>   arm64: configs: Enable sun50i cpufreq nvmem
>   arm64: dts: allwinner: h6: Enable CPU and GPU opp tables for Beelink
>     GS1
> 
> Ondrej Jirman (2):
>   arm64: dts: allwinner: h6: Add thermal trip points/cooling map
>   arm64: dts: allwinner: h6: Add CPU Operating Performance Points table
> 
> Yangtao Li (1):
>   arm64: dts: allwinner: h6: Add clock to CPU cores
> 
>  .../dts/allwinner/sun50i-h6-beelink-gs1.dts   |  10 +-
>  .../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 103 ++++++++++++++++++
>  .../boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi |  74 +++++++++++++
>  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  |  44 +++++++-
>  arch/arm64/configs/defconfig                  |   1 +
>  5 files changed, 226 insertions(+), 6 deletions(-)
>  create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
>  create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi
> 
> -- 
> 2.20.1
> 
> -- 
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Re: [linux-sunxi] [PATCH 0/7] Add support for Allwinner H6 DVFS

[Clément Péron]

Hi Ondřej,

On Sun, 5 Apr 2020 at 13:51, Ondřej Jirman <megous@megous.com> wrote:
>
> Hello Clément,
>
> On Sun, Apr 05, 2020 at 12:49:06PM +0200, Clément Péron wrote:
> > Hi Sunxi maintainers and members,
> >
> > Now that required drivers are merged we can contibute on DVFS support for
> > Allwinner H6.
> >
> > This serie is based on Yangtao Li serie[0] and Megous works[1].
> >
> > Most of the OPP tables are taken from original vendor kernel[2].
> > Plus there is a new CPU frequency @1.8GHz.
> >
> > I wrote a simple script to randomly set a frequency during a random time[3].
> > With this script and using stress-ng during a day I didn't see any issue.
> > Moreover I have tested specifically the 1.8GHz on my Beelink GS1, max thermal
> > 80°C is reached after ~10min and then the SoC oscillates quickly between 1.5
> > and 1.8GHz.
>
> Thank you for working on this. :) I wonder what SoC bin you tested this on.
>
> I have a patch to print it here:
>
>   https://megous.com/git/linux/commit/?h=ths-5.7&id=c5ddd2a45c7e04dcec31619b58de7c798ad6594c
My SoC bin is :
[    0.584553] sun50i_cpufreq_nvmem: Using CPU speed bin speed0
>
> > I also test that that offlining CPU0 and doing DVFS on other CPUs works.
> > As CPU regulator is only set for CPU0.
> >
> > But maybe it doesn't cost much to set the regulator for all the CPUs?
> >
> > Jernej test the GPU devfreq on several H6 board particulary the Tanix TX6 which
> > doesn't have a proper dedicated PMIC and doesn't had any trouble with it.
> >
> > Do you think I can enable GPU OPP for all H6 Boards?
> >
> > Also Yangtao Li enable DVFS for OrangePi and Pine64, as I can't test them I
> > didn't reenable these boards. Please, let me know if you want me to add these
> > boards in this serie.
>
> Feel free to add these OPPs also to OrangePi 3 dts, I've been running mine with
> this OPP table for at least a year already (I have the worst SoC bin).
>
> Though I'll run a bit more comprehensive test for more frequencies, like you
> did, just to be sure.
>
> One thing I wonder about is if there should not be some small ramp delay on the
> CPU regulator node, because voltage change probably takes some small time to
> apply, compared to changing the PLL frequency. And I have no idea if the CPU
> is not running for some very small time out of spec during transitions.
>
> I didn't find timing information in the PMIC datasheet, but I suppose based
> on the DCDCA frequency of 3MHz that it will adapt to the new voltage in the
> range of 1s-10s of microseconds.
>
> In datasheet of the similar PMIC (AXP813) there is this note:
>
>   DVM (Dynamic Voltage scaling Management) ramp rate: 2.5mV/us at buck frequency 3MHz

Good point, this information should be added for both CPU and GPU regulator.
This could be nice to confirm this point with a scope.

Also I remark that Allwinner user higher temperature than what we set :
alarm_low_temp = <105000>;
alarm_high_temp = <110000>;
alarm_temp_hysteresis = <15000>;
shut_temp= <115000>;
https://github.com/orangepi-xunlong/OrangePiH6_Linux4_9/blob/master/arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi#L1924

Don't you think that we can push a bit higher the temperature it's
actually at 80°C ?

Thanks for the review,
Clement

>
> I think it will be simiar with AXP805.
>
> regards,
>         o.
>
> > Thanks,
> > Clément
> >
> > 0: https://patchwork.kernel.org/cover/10815117/
> > 1: https://megous.com/git/linux/log/?h=ths-5.7
> > 2: https://github.com/orangepi-xunlong/OrangePiH6_Linux4_9/blob/master/arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi#L345-L517
> > 3: https://gist.github.com/clementperon/55a055dae3f13bbd14fb39c0069fe2e2
> >
> > Clément Péron (4):
> >   arm64: dts: allwinner: h6: set thermal polling time
> >   arm64: dts: allwinner: h6: Add GPU Operating Performance Points table
> >   arm64: configs: Enable sun50i cpufreq nvmem
> >   arm64: dts: allwinner: h6: Enable CPU and GPU opp tables for Beelink
> >     GS1
> >
> > Ondrej Jirman (2):
> >   arm64: dts: allwinner: h6: Add thermal trip points/cooling map
> >   arm64: dts: allwinner: h6: Add CPU Operating Performance Points table
> >
> > Yangtao Li (1):
> >   arm64: dts: allwinner: h6: Add clock to CPU cores
> >
> >  .../dts/allwinner/sun50i-h6-beelink-gs1.dts   |  10 +-
> >  .../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 103 ++++++++++++++++++
> >  .../boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi |  74 +++++++++++++
> >  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  |  44 +++++++-
> >  arch/arm64/configs/defconfig                  |   1 +
> >  5 files changed, 226 insertions(+), 6 deletions(-)
> >  create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
> >  create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi
> >
> > --
> > 2.20.1
> >
> > --
> > You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
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Re: [linux-sunxi] [PATCH 0/7] Add support for Allwinner H6 DVFS

[Ondřej Jirman]

Hi,

On Sun, Apr 05, 2020 at 04:33:37PM +0200, Clément Péron wrote:
> Hi Ondřej,

[ ... ]

> Good point, this information should be added for both CPU and GPU regulator.
> This could be nice to confirm this point with a scope.
> 
> Also I remark that Allwinner user higher temperature than what we set :
> alarm_low_temp = <105000>;
> alarm_high_temp = <110000>;
> alarm_temp_hysteresis = <15000>;
> shut_temp= <115000>;
> https://github.com/orangepi-xunlong/OrangePiH6_Linux4_9/blob/master/arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi#L1924
> 
> Don't you think that we can push a bit higher the temperature it's
> actually at 80°C ?

We probably can. But just 5°C between high temp and criticla temp is probably
not enough. I'd probably set our value to something like 90-100°C so that quick
temperature spike before regulation kicks in would not shutdown the CPU.

regards,
	o.

> Thanks for the review,
> Clement
> 

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Re: [linux-sunxi] [PATCH 0/7] Add support for Allwinner H6 DVFS

[Clément Péron]

Hi,

On Sun, 5 Apr 2020 at 16:54, Ondřej Jirman <megous@megous.com> wrote:
>
> Hi,
>
> On Sun, Apr 05, 2020 at 04:33:37PM +0200, Clément Péron wrote:
> > Hi Ondřej,
>
> [ ... ]
>
> > Good point, this information should be added for both CPU and GPU regulator.
> > This could be nice to confirm this point with a scope.
> >
> > Also I remark that Allwinner user higher temperature than what we set :
> > alarm_low_temp = <105000>;
> > alarm_high_temp = <110000>;
> > alarm_temp_hysteresis = <15000>;
> > shut_temp= <115000>;
> > https://github.com/orangepi-xunlong/OrangePiH6_Linux4_9/blob/master/arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi#L1924
> >
> > Don't you think that we can push a bit higher the temperature it's
> > actually at 80°C ?
>
> We probably can. But just 5°C between high temp and criticla temp is probably
> not enough. I'd probably set our value to something like 90-100°C so that quick
> temperature spike before regulation kicks in would not shutdown the CPU.

OK I will push it to 85°C and leave the critical to 100°C.

Test it again and will send a v2

Regards,
Clément

>
> regards,
>         o.
>
> > Thanks for the review,
> > Clement
> >

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Re: [PATCH 0/7] Add support for Allwinner H6 DVFS

[Clément Péron]

Hi,

On Sun, 5 Apr 2020 at 12:49, Clément Péron <peron.clem@gmail.com> wrote:
>
> Hi Sunxi maintainers and members,
>
> Now that required drivers are merged we can contibute on DVFS support for
> Allwinner H6.
>
> This serie is based on Yangtao Li serie[0] and Megous works[1].
>
> Most of the OPP tables are taken from original vendor kernel[2].
> Plus there is a new CPU frequency @1.8GHz.
>
> I wrote a simple script to randomly set a frequency during a random time[3].
> With this script and using stress-ng during a day I didn't see any issue.
> Moreover I have tested specifically the 1.8GHz on my Beelink GS1, max thermal
> 80°C is reached after ~10min and then the SoC oscillates quickly between 1.5
> and 1.8GHz.
This result is wrong ignore it.

I will resend new one in next serie.

Regards,
Clement
>
> I also test that that offlining CPU0 and doing DVFS on other CPUs works.
> As CPU regulator is only set for CPU0.
>
> But maybe it doesn't cost much to set the regulator for all the CPUs?
>
> Jernej test the GPU devfreq on several H6 board particulary the Tanix TX6 which
> doesn't have a proper dedicated PMIC and doesn't had any trouble with it.
>
> Do you think I can enable GPU OPP for all H6 Boards?
>
> Also Yangtao Li enable DVFS for OrangePi and Pine64, as I can't test them I
> didn't reenable these boards. Please, let me know if you want me to add these
> boards in this serie.
>
> Thanks,
> Clément
>
> 0: https://patchwork.kernel.org/cover/10815117/
> 1: https://megous.com/git/linux/log/?h=ths-5.7
> 2: https://github.com/orangepi-xunlong/OrangePiH6_Linux4_9/blob/master/arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi#L345-L517
> 3: https://gist.github.com/clementperon/55a055dae3f13bbd14fb39c0069fe2e2
>
> Clément Péron (4):
>   arm64: dts: allwinner: h6: set thermal polling time
>   arm64: dts: allwinner: h6: Add GPU Operating Performance Points table
>   arm64: configs: Enable sun50i cpufreq nvmem
>   arm64: dts: allwinner: h6: Enable CPU and GPU opp tables for Beelink
>     GS1
>
> Ondrej Jirman (2):
>   arm64: dts: allwinner: h6: Add thermal trip points/cooling map
>   arm64: dts: allwinner: h6: Add CPU Operating Performance Points table
>
> Yangtao Li (1):
>   arm64: dts: allwinner: h6: Add clock to CPU cores
>
>  .../dts/allwinner/sun50i-h6-beelink-gs1.dts   |  10 +-
>  .../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 103 ++++++++++++++++++
>  .../boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi |  74 +++++++++++++
>  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  |  44 +++++++-
>  arch/arm64/configs/defconfig                  |   1 +
>  5 files changed, 226 insertions(+), 6 deletions(-)
>  create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
>  create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi
>
> --
> 2.20.1
>

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