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Mon, 20 Apr 2020 03:38:44 -0400 (EDT) Date: Mon, 20 Apr 2020 09:38:42 +0200 From: Maxime Ripard To: Philipp Rossak Subject: Re: [PATCH v6 00/12] ARM/MIPS: DTS: add child nodes describing the PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more) Message-ID: <20200420073842.nx4xb3zqvu23arkc@gilmour.lan> References: <20200415101008.zxzxca2vlfsefpdv@gilmour.lan> <2E3401F1-A106-4396-8FE6-51CAB72926A4@goldelico.com> <20200415130233.rgn7xrtwqicptke2@gilmour.lan> <10969e64-fe1f-d692-4984-4ba916bd2161@gmail.com> MIME-Version: 1.0 In-Reply-To: <10969e64-fe1f-d692-4984-4ba916bd2161@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200420_003853_935133_0E3881F0 X-CRM114-Status: GOOD ( 25.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , David Airlie , "H. Nikolaus Schaller" , "open list:DRM PANEL DRIVERS" , linux-mips@vger.kernel.org, Paul Cercueil , linux-samsung-soc@vger.kernel.org, Discussions about the Letux Kernel , Paul Burton , Krzysztof Kozlowski , Tony Lindgren , Chen-Yu Tsai , Kukjin Kim , James Hogan , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , =?utf-8?Q?Beno=C3=AEt?= Cousson , Rob Herring , linux-omap , arm-soc , Thomas Bogendoerfer , OpenPVRSGX Linux Driver Group , Linux Kernel Mailing List , Ralf Baechle , Daniel Vetter , kernel@pyra-handheld.com Content-Type: multipart/mixed; boundary="===============6769612419502934555==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============6769612419502934555== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="nd4xfztpubexblrg" Content-Disposition: inline --nd4xfztpubexblrg Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Fri, Apr 17, 2020 at 02:09:06PM +0200, Philipp Rossak wrote: > > > I'm a bit skeptical on that one since it doesn't even list the > > > interrupts connected to the GPU that the binding mandates. > >=20 > > I think he left it out for a future update. > > But best he comments himself. >=20 > I'm currently working on those bindings. They are now 90% done, but they = are > not finished till now. Currently there is some mainline support missing to > add the full binding. The A83T and also the A31/A31s have a GPU Power Off > Gating Register in the R_PRCM module, that is not supported right now in > Mainline. The Register need to be written when the GPU is powered on and > off. >=20 > @Maxime: I totally agree on your point that a demo needs to be provided > before the related DTS patches should be provided. That's the reason why I > added the gpu placeholder patches. > Do you have an idea how a driver for the R_PRCM stuff can look like? I'm = not > that experienced with the clock driver framework. It looks like a power-domain to me, so you'd rather plug that into the genpd framework. > The big question is right now how to proceed with the A83T and A31s patch= es. > I see there three options, which one do you prefer?: >=20 > 1. Provide now placeholder patches and send new patches, if everything is > clear and other things are mainlined > 2. Provide now patches as complete as possible and provide later patches = to > complete them when the R_PRCM things are mainlined > 3. Leave them out, till the related work is mainlined and the bindings are > final. Like I said, the DT *has* to be backward-compatible, so for any DT patch th= at you are asking to be merged, you should be prepared to support it indefinit= ely and be able to run from it, and you won't be able to change the bindings la= ter on. > Since this GPU IP core is very flexible and the SOC manufactures can > configure it on their needs, I think the binding will extend in the futur= e. > For example the SGX544 GPU is available in different configurations: there > is a SGX544 core and SGX544MPx core. The x stands for the count of the US= SE > (Universal Scalable Shader Engine) cores. For example the GPU in the A83T= is > a MP1 and the A31/A31s a MP2. Mali is in the same situation and it didn't cause much trouble. > In addition to that some of the GPU's have also a 2D engine. In the same memory region, running from the same interrupts, or is it a completely separate IP that happens to be sold by the same vendor? > There might be even more differences in the GPU's that we don't know right > now and should be described in the Devicetree, but that's a different top= ic > that we should keep in mind. Like I said, it's not a completely different topic. Maxime --nd4xfztpubexblrg Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXp1RggAKCRDj7w1vZxhR xUoGAQD6t2KhRl/JXPpcbOq2qYAidBLKV4Lqvkk8MmRHUxeoNQEAt6SP6CIMrrfb nDX66jY4FpmurrYXbFF39NVW4Y9HWw8= =Wz+7 -----END PGP SIGNATURE----- --nd4xfztpubexblrg-- --===============6769612419502934555== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============6769612419502934555==--