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Wed, 22 Apr 2020 05:23:02 -0400 (EDT) Date: Wed, 22 Apr 2020 11:23:00 +0200 From: Maxime Ripard To: Jernej =?utf-8?Q?=C5=A0krabec?= Subject: Re: [PATCH] drm/sun4i: hdmi ddc clk: Fix size of m divider Message-ID: <20200422092300.444wcaurdwyrorow@gilmour.lan> References: <20200413095457.1176754-1-jernej.skrabec@siol.net> <1742537.tdWV9SEqCh@jernej-laptop> <20200415104214.ndkkxfnufkxgu53r@gilmour.lan> <1785843.taCxCBeP46@jernej-laptop> MIME-Version: 1.0 In-Reply-To: <1785843.taCxCBeP46@jernej-laptop> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200422_022313_660846_C2DBC9D9 X-CRM114-Status: GOOD ( 26.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , linux-kernel , dri-devel , Chen-Yu Tsai , Daniel Vetter , linux-arm-kernel Content-Type: multipart/mixed; boundary="===============1218797080346812370==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============1218797080346812370== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="7oskm5d3tnjhoykn" Content-Disposition: inline --7oskm5d3tnjhoykn Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Wed, Apr 15, 2020 at 07:52:28PM +0200, Jernej =C5=A0krabec wrote: > Dne sreda, 15. april 2020 ob 12:42:14 CEST je Maxime Ripard napisal(a): > > On Mon, Apr 13, 2020 at 06:09:08PM +0200, Jernej =C5=A0krabec wrote: > > > Dne ponedeljek, 13. april 2020 ob 16:12:39 CEST je Chen-Yu Tsai=20 > napisal(a): > > > > On Mon, Apr 13, 2020 at 6:11 PM Chen-Yu Tsai wrote: > > > > > On Mon, Apr 13, 2020 at 5:55 PM Jernej Skrabec > > > > > > > >=20 > > > wrote: > > > > > > m divider in DDC clock register is 4 bits wide. Fix that. > > > > > >=20 > > > > > > Fixes: 9c5681011a0c ("drm/sun4i: Add HDMI support") > > > > > > Signed-off-by: Jernej Skrabec > > > > >=20 > > > > > Reviewed-by: Chen-Yu Tsai > > > >=20 > > > > Cc stable? > > >=20 > > > I don't think it's necessary: > > > 1. It doesn't change much (anything?) for me when reading EDID. I don= 't > > > think it's super important to have precise DDC clock in order to prop= erly > > > read EDID. 2. No matter if it has "Cc stable" tag or not, it will be > > > eventually picked for stable due to fixes tag. > > >=20 > > > This was only small observation when I was researching EDID readout i= ssue > > > on A20 board, but sadly, I wasn't able to figure out why reading it > > > sometimes fails. I noticed similar issue on SoCs with DE2 (most > > > prominently on OrangePi PC2 - H5), but there was easy workaround - I = just > > > disabled video driver in U- Boot. However, if A20 display driver gets > > > disabled in U-Boot, it totally breaks video output on my TV when Linux > > > boots (no output). I guess there is more fundamental problem with clo= cks > > > than just field size. I think we should add more constraints in clock > > > driver, like preset some clock parents and not allow to change parents > > > when setting rate, but carefully, so simplefb doesn't break. Such > > > constraints should also solve problems with dual head setups. > > I disagree here. Doing all sorts of special case just doesn't scale, > > and we'll never have the special cases sorted out on all the boards > > (and it's a nightmare to maintain). > >=20 > > Especially since it's basically putting a blanket over the actual > > issue and looking the other way. If there's something wrong with how > > we deal with (re)parenting, we should fix that. It impacts more than > > just DRM, and all the SoCs. >=20 > I agree with you that automatic solution would be best, but I just don't = see > it how it would be done. > Dual head display pipeline is pretty complex for clock driver to get it r= ight > on it's own. There are different possible setups and some of them are hot > pluggable, like HDMI. Do you have an actual scenario that is broken right now? > And there are also SoC specific quirks, like A64, where for some reason, = MIPI > DPHY and HDMI PHY share same clock parent - PLL_VIDEO0. Technically, MIPI= DPHY > can be clocked from PLL_PERIPH0 (fixed to 600 MHz), but that's not really > helpful. I'm not even sure if there is any good solution to this - certai= nly > HDMI and MIPI can't claim exclusivity and somehow best common rate must be > found for PLL_VIDEO0, if that's even possible. IIRC the DSI DPHY needs a clock running at 297MHz, which is pretty much wha= t the HDMI PHY should need too (or 148.5, but that's pretty easy to generate from 297). So which problem do we have there? > I was sure that HDMI PHY on A64 can be clocked from PLL_VIDEO1, which wou= ld > solve main issue, but to date, I didn't find any way to do that. >=20 > That's pretty off topic, so I hope original patch can be merged as-is. It does, sorry Acked-by: Maxime Ripard Maxime --7oskm5d3tnjhoykn Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXqAM9AAKCRDj7w1vZxhR xTmVAP9kvmX4WaSBtV/XQiF2vUsWwoTSx6VEdAN+fmPtFRk1AAEAmRVLotyUAtrH emjt+9TNkeEsYLIWoTgSrr6rcGDv8QQ= =JYMX -----END PGP SIGNATURE----- --7oskm5d3tnjhoykn-- --===============1218797080346812370== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============1218797080346812370==--