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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jRZFw-0002fC-VY; Thu, 23 Apr 2020 10:38:56 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jRZFt-0002ek-A3 for linux-arm-kernel@lists.infradead.org; Thu, 23 Apr 2020 10:38:55 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1520531B; Thu, 23 Apr 2020 03:38:52 -0700 (PDT) Received: from gaia (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A54943F68F; Thu, 23 Apr 2020 03:38:50 -0700 (PDT) Date: Thu, 23 Apr 2020 11:38:48 +0100 From: Catalin Marinas To: linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3 10/23] arm64: mte: Handle synchronous and asynchronous tag check faults Message-ID: <20200423103847.GC4963@gaia> References: <20200421142603.3894-1-catalin.marinas@arm.com> <20200421142603.3894-11-catalin.marinas@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200421142603.3894-11-catalin.marinas@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200423_033854_336151_9F545DB4 X-CRM114-Status: GOOD ( 11.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, Richard Earnshaw , Szabolcs Nagy , Andrey Konovalov , Kevin Brodsky , Peter Collingbourne , linux-mm@kvack.org, Vincenzo Frascino , Will Deacon Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Apr 21, 2020 at 03:25:50PM +0100, Catalin Marinas wrote: > diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S > index ddcde093c433..3650a0a77ed0 100644 > --- a/arch/arm64/kernel/entry.S > +++ b/arch/arm64/kernel/entry.S > @@ -145,6 +145,31 @@ alternative_cb_end > #endif > .endm > > + /* Check for MTE asynchronous tag check faults */ > + .macro check_mte_async_tcf, flgs, tmp > +#ifdef CONFIG_ARM64_MTE > +alternative_if_not ARM64_MTE > + b 1f > +alternative_else_nop_endif > + mrs_s \tmp, SYS_TFSRE0_EL1 > + tbz \tmp, #SYS_TFSR_EL1_TF0_SHIFT, 1f > + /* Asynchronous TCF occurred for TTBR0 access, set the TI flag */ > + orr \flgs, \flgs, #_TIF_MTE_ASYNC_FAULT > + str \flgs, [tsk, #TSK_TI_FLAGS] > + msr_s SYS_TFSRE0_EL1, xzr > +1: > +#endif > + .endm > + > + /* Clear the MTE asynchronous tag check faults */ > + .macro clear_mte_async_tcf > +#ifdef CONFIG_ARM64_MTE > +alternative_if ARM64_MTE > + msr_s SYS_TFSRE0_EL1, xzr > +alternative_else_nop_endif This needs a 'dsb ish' prior to the msr as an indirect write (async tag check fault) to the TFSRE0_EL1 register is not ordered with a subsequent direct write (msr) to this register. The check_mte_async_tcf macro is fine as we execute it after taking an exception with SCTLR_EL1.ITFSB bit set (which triggers such synchronisation). -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel