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Thu, 23 Apr 2020 16:36:44 -0400 (EDT) Date: Thu, 23 Apr 2020 22:36:42 +0200 From: Maxime Ripard To: "H. Nikolaus Schaller" Subject: Re: [PATCH v6 00/12] ARM/MIPS: DTS: add child nodes describing the PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more) Message-ID: <20200423203642.35ms4aarnv65tfp5@gilmour.lan> References: <20200421112129.zjmkmzo3aftksgka@gilmour.lan> <20200421141543.GU37466@atomide.com> <20200422065859.quy6ane5v7vsy5tf@gilmour.lan> <1AA57A0C-48E6-49BB-BB9A-2AAFFB371BCD@goldelico.com> <20200422151328.2oyqz7gqkbunmd6o@gilmour.lan> <07923B6C-4CCD-4B81-A98F-E19C43412A89@goldelico.com> <43688597-4b99-8f4d-9ad5-548ddff07f52@baylibre.com> <71F2F964-32C7-41E6-8F1A-A73161EA1BB3@goldelico.com> MIME-Version: 1.0 In-Reply-To: <71F2F964-32C7-41E6-8F1A-A73161EA1BB3@goldelico.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200423_133702_380101_F99153AD X-CRM114-Status: GOOD ( 21.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Neil Armstrong , Tony Lindgren , James Hogan , Jonathan Bakker , "open list:DRM PANEL DRIVERS" , Linux Kernel Mailing List , Paul Cercueil , linux-samsung-soc@vger.kernel.org, Paul Burton , Krzysztof Kozlowski , David Airlie , Chen-Yu Tsai , Kukjin Kim , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , =?utf-8?Q?Beno=C3=AEt?= Cousson , Rob Herring , linux-omap , arm-soc , Thomas Bogendoerfer , Philipp Rossak , OpenPVRSGX Linux Driver Group , linux-mips@vger.kernel.org, Ralf Baechle , Daniel Vetter , kernel@pyra-handheld.com, Discussions about the Letux Kernel Content-Type: multipart/mixed; boundary="===============1517417578913194562==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============1517417578913194562== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="goo77pyirkr5psgn" Content-Disposition: inline --goo77pyirkr5psgn Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Apr 23, 2020 at 05:45:55PM +0200, H. Nikolaus Schaller wrote: > > Am 23.04.2020 um 17:00 schrieb Neil Armstrong : > >> One thing we can learn is that "core" seems to be a de facto standard= =20 > >> for the core clock-name. An alternative "gpu" is used by nvidia,gk20a.= txt. > >=20 > > Usually IPs needs a few clocks: > > - pclk or apb or reg: the clock clocking the "slave" bus to serve the r= egisters > > - axi or bus or ahb: the bus clocking the the "master" bus to get data = =66rom system memory > > - core: the actual clock feeding the GPU logic >=20 > And the sgx544 seems to have two such clocks. >=20 > > Sometimes you have a single clock for slave and master bus. > >=20 > > But you can also have separate clocks for shader cores, .. this depends= on the IP and it's architecture. > > The IP can also have memories with separate clocks, etc... >=20 > Indeed. >=20 > > But all these clocks can be source by an unique clock on a SoC, but dif= ferent on another > > SoC, this is why it's important to list them all, even optional. > >=20 > > You'll certainly have at least a reset signal, and a power domain, thes= e should exist and be optional. >=20 > Well, they exist only as hints in block diagrams of some SoC data > sheets (so we do not know if they represent the imagination > definitions) and the current driver code doesn't make use of it. Still > the gpu core works. >=20 > So I do not see any urgent need to add a complete list to the bindings > now. >=20 > Unless some special SoC integration makes use of them. Then it is IMHO > easier to extend the bindings by a follow-up patch than now thinking > about all potential options and bloating the bindings with things we > (the open source community) doesn't and can't know. >=20 > My goal is to keep the bindings as minimalistic as possible. And reset > lines and power domains are (at least for those we have in the works) > not needed to make working systems. >=20 > Therefore, for clocks I also would start with a minimalistic approach > for a single optional GPU core clock and leave out reset and power > completely. Like I said above, the DT is considered an ABI and you'll have to maintain backward compatibility (ie, newer kernel running with older DT). Therefore, you won't be able to require a new clock, reset or power-domain later on for example. I guess the question I'm really asking is: since you don't really know how the hardware is integrated at the moment, why should we have that discussion *now*. It's really not suprising that you don't know yet, so I'm not sure why we need to rush in the bindings. Maxime --goo77pyirkr5psgn Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXqH8WgAKCRDj7w1vZxhR xevnAQDosUT6nmUX0+zNQOj7IKsbVGpyycJhdLX1FoaJiEMTHgD/SWTr0aPp/w2C TCfnfiPupaeG8u9JV8QMCk/a58o6Xw8= =ygqv -----END PGP SIGNATURE----- --goo77pyirkr5psgn-- --===============1517417578913194562== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============1517417578913194562==--