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Thu, 30 Apr 2020 02:27:02 -0700 (PDT) Date: Thu, 30 Apr 2020 10:26:58 +0100 From: Andrew Scull To: Marc Zyngier Subject: Re: [PATCH v2] arm64: Unify WORKAROUND_SPECULATIVE_AT_{NVHE,VHE} Message-ID: <20200430092658.GF15669@google.com> References: <20200422161346.67325-1-ascull@google.com> <20200429212120.GC8604@willie-the-truck> <5f391a75142a8ae2263e52d37d73526d@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <5f391a75142a8ae2263e52d37d73526d@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200430_022708_489292_F2C1CA13 X-CRM114-Status: GOOD ( 19.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Suzuki K Poulose , Steven Price , James Morse , Will Deacon , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Apr 30, 2020 at 10:16:03AM +0100, Marc Zyngier wrote: > On 2020-04-29 22:21, Will Deacon wrote: > > Hi Andrew, > > > > On Wed, Apr 22, 2020 at 05:13:46PM +0100, Andrew Scull wrote: > > > Errata 1165522, 1319367 and 1530923 each allow TLB entries to be > > > allocated as a result of a speculative AT instruction. In order to > > > avoid mandating VHE on certain affected CPUs, apply the workaround to > > > both the nVHE and the VHE case for all affected CPUs. > > > > > > Signed-off-by: Andrew Scull > > > CC: Marc Zyngier > > > CC: James Morse > > > CC: Suzuki K Poulose > > > CC: Will Deacon > > > CC: Steven Price > > > --- > > > * From v1 <20200327143941.195626-1-ascull@google.com>: > > > - Restored registers in VHE path > > > > This largely looks good to me, but I don't understand these bits: > > > > > diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c > > > index 8a1e81a400e0..651820f537fb 100644 > > > --- a/arch/arm64/kvm/hyp/switch.c > > > +++ b/arch/arm64/kvm/hyp/switch.c > > > @@ -138,7 +138,7 @@ static void __hyp_text > > > __activate_traps_nvhe(struct kvm_vcpu *vcpu) > > > > > > write_sysreg(val, cptr_el2); > > > > > > - if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT_NVHE)) { > > > + if (cpus_have_const_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { > > > > It seems like you consistently replace cpus_have_final_cap() with > > cpus_have_const_cap(), but I can't figure out why that's required. > > Seems like a bad conflict resolution. We definitely want to keep the > final_cap checks for anything that will run at EL2, and probably > everywhere else (if capabilities are not final by the time we hit KVM, > we have bigger problems to solve). > > Thanks, > > M. > -- > Jazz is not dead. It just smells funny... Indeed, those weren't the 5 characters my eye was interested in. Looks like we'll be having a v3.. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel