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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Apr 21, 2020 at 02:31:53PM +0800, Shaokun Zhang wrote: > Some new PMU events can been detected by PMCEID1_EL0, but it can't > be listed, Let's expose these through sysfs. > > Cc: Will Deacon > Cc: Mark Rutland > Signed-off-by: Shaokun Zhang > --- > arch/arm64/include/asm/perf_event.h | 19 +++++++++++++++++++ > arch/arm64/kernel/perf_event.c | 19 +++++++++++++++++++ > 2 files changed, 38 insertions(+) > > diff --git a/arch/arm64/include/asm/perf_event.h b/arch/arm64/include/asm/perf_event.h > index e7765b62c712..f1b93d7c4260 100644 > --- a/arch/arm64/include/asm/perf_event.h > +++ b/arch/arm64/include/asm/perf_event.h > @@ -72,12 +72,31 @@ > #define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD 0x36 > #define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD 0x37 > #define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD 0x38 > +#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD 0x39 > +#define ARMV8_PMUV3_PERFCTR_OP_RETIRED 0x3A > +#define ARMV8_PMUV3_PERFCTR_OP_SPEC 0x3B > +#define ARMV8_PMUV3_PERFCTR_STALL 0x3C > +#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND 0x3D > +#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND 0x3E > +#define ARMV8_PMUV3_PERFCTR_STALL_SLOT 0x3F Hmm, looks like the presence of this event implies the presence of the PMMIR_EL1 register. Should we be exposing the "SLOTS" field from that in sysfs? (obviously as a separate patch) > > /* Statistical profiling extension microarchitectural events */ > #define ARMV8_SPE_PERFCTR_SAMPLE_POP 0x4000 > #define ARMV8_SPE_PERFCTR_SAMPLE_FEED 0x4001 > #define ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE 0x4002 > #define ARMV8_SPE_PERFCTR_SAMPLE_COLLISION 0x4003 > +#define ARMV8_SPE_PERFCTR_CNT_CYCLES 0x4004 > +#define ARMV8_SPE_PERFCTR_STALL_BACKEND_MEM 0x4005 > +#define ARMV8_SPE_PERFCTR_L1I_CACHE_LMISS 0x4006 > +#define ARMV8_SPE_PERFCTR_L2D_CACHE_LMISS_RD 0x4009 > +#define ARMV8_SPE_PERFCTR_L2I_CACHE_LMISS 0x400A > +#define ARMV8_SPE_PERFCTR_L3D_CACHE_LMISS_RD 0x400B > +#define ARMV8_SPE_PERFCTR_LDST_ALIGN_LAT 0x4020 > +#define ARMV8_SPE_PERFCTR_LD_ALIGN_LAT 0x4021 > +#define ARMV8_SPE_PERFCTR_ST_ALIGN_LAT 0x4022 > +#define ARMV8_SPE_PERFCTR_MEM_ACCESS_CHECKED 0x4024 > +#define ARMV8_SPE_PERFCTR_MEM_ACCESS_CHECKED_RD 0x4025 > +#define ARMV8_SPE_PERFCTR_MEM_ACCESS_CHECKED_WR 0x4026 I think the naming is off here, as these don't seem to have anything to do with SPE afaict. Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel