From: Will Deacon <will@kernel.org>
To: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: Yuqi Jin <jinyuqi@huawei.com>,
Andrew Murray <amurray@thegoodpenguin.co.uk>,
linux-arm-kernel@lists.infradead.org,
Catalin Marinas <catalin.marinas@arm.com>
Subject: Re: [PATCH] arm64: atomics: Fix the issue on xchg when switch to atomic instruction
Date: Tue, 5 May 2020 10:15:03 +0100 [thread overview]
Message-ID: <20200505091503.GC16980@willie-the-truck> (raw)
In-Reply-To: <1588669355-38741-1-git-send-email-zhangshaokun@hisilicon.com>
On Tue, May 05, 2020 at 05:02:35PM +0800, Shaokun Zhang wrote:
> From: Yuqi Jin <jinyuqi@huawei.com>
>
> Since commit addfc38672c7 ("arm64: atomics: avoid out-of-line ll/sc atomics"),
> it has provided inline implementations of both LSE and ll/sc and used a static
> key to select between them, which allows the compiler to generate better
> atomics code.
> However, xchg still uses the original method which would fail to switch to
> the atomic instruction correctly, Let's fix this issue.
Please can you elaborate on the failure mode? The current code looks alright
to me, so I'm clearly missing something. What's broken?
Will
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next prev parent reply other threads:[~2020-05-05 9:15 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-05 9:02 [PATCH] arm64: atomics: Fix the issue on xchg when switch to atomic instruction Shaokun Zhang
2020-05-05 9:15 ` Will Deacon [this message]
2020-05-06 7:00 ` Shaokun Zhang
2020-05-06 7:53 ` Will Deacon
2020-05-06 10:39 ` Shaokun Zhang
2020-05-06 10:44 ` Will Deacon
2020-05-06 11:30 ` Shaokun Zhang
2020-05-07 7:54 ` Shaokun Zhang
2020-05-25 9:27 ` Shaokun Zhang
2020-05-26 19:55 ` Will Deacon
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