From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2185CCA90AF for ; Tue, 12 May 2020 17:33:13 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CF1C8206B8 for ; Tue, 12 May 2020 17:33:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="ZFyvW3XZ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CF1C8206B8 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=3noF+blZon54BZiMNUyiD8twZdXgZs2IF76GJqBexn0=; b=ZFyvW3XZs/3BNa GL0m7YymWZ3/7L1D9Rz4iP8DDluNqWGJ9ZWnzt/c6natt1f97W/Ekh736qYS7G6vyZqwdMQdQI4Sv 3RM+KR3QeBFthXzjK8WDr8vNttvdGYa4GZv38kkAtXNlUVpNn1d2NZHVmnQJWx/ZPEsFPkWTo/t+b jxv4EXRhFOqc5kZULiF6BnuKR1tlipTzpFrpX4YGMIjn6BYKrZnw9GL1D8uitKPswSxUrMIeetOfh a4tKyMLYiX/EG+hLcL9udYFuLBUJkBR/qtavGg8DS6c1a0+ITqbAW04EQDrkDamP5IxgVG1BVzUV0 QXoHUJqXpL1TzWHKp30A==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jYYmG-0004QR-4R; Tue, 12 May 2020 17:33:12 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jYYmC-0004Q6-Ux for linux-arm-kernel@lists.infradead.org; Tue, 12 May 2020 17:33:10 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5129A1FB; Tue, 12 May 2020 10:33:08 -0700 (PDT) Received: from C02TF0J2HF1T.local (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 018FD3F305; Tue, 12 May 2020 10:33:04 -0700 (PDT) Date: Tue, 12 May 2020 18:33:01 +0100 From: Catalin Marinas To: Amit Kachhap Subject: Re: [PATCH v2 3/4] arm64: cpufeature: Modify address authentication cpufeature to exact Message-ID: <20200512173301.GB21213@C02TF0J2HF1T.local> References: <1586842314-19527-1-git-send-email-amit.kachhap@arm.com> <1586842314-19527-4-git-send-email-amit.kachhap@arm.com> <20200506171350.GH2878@gaia> <426d96ef-6a89-6ee5-c0e0-383b297f7f9f@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <426d96ef-6a89-6ee5-c0e0-383b297f7f9f@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200512_103309_083169_3BB319C6 X-CRM114-Status: GOOD ( 22.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Kees Cook , Suzuki K Poulose , Kristina Martsenko , Mark Brown , James Morse , Vincenzo Frascino , Will Deacon , Dave Martin , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, May 08, 2020 at 09:51:53PM +0530, Amit Kachhap wrote: > On 5/6/20 10:43 PM, Catalin Marinas wrote: > > On Tue, Apr 14, 2020 at 11:01:53AM +0530, Amit Daniel Kachhap wrote: > > > This patch modifies the address authentication cpufeature type to EXACT > > > from earlier LOWER_SAFE as the different configurations added for Armv8.6 > > > enhanced PAC have different behaviour and there is no tunable to enable the > > > lower safe versions. The safe value is set as 0. > > > > > > After this change, if there is any variation in configurations in secondary > > > cpus from boot cpu then those cpus are marked tainted. The KVM guests may > > > completely disable address authentication if there is any such variations > > > detected. > > > > > > Signed-off-by: Amit Daniel Kachhap > > > --- > > > arch/arm64/kernel/cpufeature.c | 4 ++-- > > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > > > index 08795025409c..599b03df2f93 100644 > > > --- a/arch/arm64/kernel/cpufeature.c > > > +++ b/arch/arm64/kernel/cpufeature.c > > > @@ -154,9 +154,9 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { > > > ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), > > > ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), > > > ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), > > > - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0), > > > + FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0), > > > ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), > > > - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0), > > > + FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0), > > > ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0), > > > ARM64_FTR_END, > > > > Is this sufficient? If we have the boot CPU already enabling the ptrauth > > and we get a secondary CPU with a different ISAR1 field that matches the > > address auth in cpufeature.c, we still allow it to boot. We no longer > > report the feature to the user system_supports_address_auth() is true > > while system_supports_generic_auth() would be false as it checks the > > sanitised feature registers. > > Yes agreed. Generic authentication also needs EXACT cpufeature type. I'm still not sure that's sufficient. If we boot the primary CPU with ptrauth as detected in proc.S, we consider this a boot feature so all secondary CPUs must have it. Subsequent CPUs are currently checked via the arm64_features[] definitions and we allow them to boot if the ID is at least that of the boot CPU. How does this interact with the above FTR_EXACT changes? My concern is that we boot with PAC enabled on all CPUs but because of the FTR_EXACT, the sanitised ID registers no longer report the feature. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel