Re: [PATCH v3 10/23] arm64: mte: Handle synchronous and asynchronous tag check faults

Catalin Marinas
2020-04-23T10:39:01Z

On Tue, Apr 21, 2020 at 03:25:50PM +0100, Catalin Marinas wrote:
> diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
> index ddcde093c433..3650a0a77ed0 100644
> --- a/arch/arm64/kernel/entry.S
> +++ b/arch/arm64/kernel/entry.S
> @@ -145,6 +145,31 @@ alternative_cb_end
> #endif
> .endm
>
> + /* Check for MTE asynchronous tag check faults */
> + .macro check_mte_async_tcf, flgs, tmp
> +#ifdef CONFIG_ARM64_MTE
> +alternative_if_not ARM64_MTE
> + b 1f
> +alternative_else_nop_endif
> + mrs_s \tmp, SYS_TFSRE0_EL1
> + tbz \tmp, #SYS_TFSR_EL1_TF0_SHIFT, 1f
> + /* Asynchronous TCF occurred for TTBR0 access, set the TI flag */
> + orr \flgs, \flgs, #_TIF_MTE_ASYNC_FAULT
> + str \flgs, [tsk, #TSK_TI_FLAGS]
> + msr_s SYS_TFSRE0_EL1, xzr
> +1:
> +#endif
> + .endm
> +
> + /* Clear the MTE asynchronous tag check faults */
> + .macro clear_mte_async_tcf
> +#ifdef CONFIG_ARM64_MTE
> +alternative_if ARM64_MTE
> + msr_s SYS_TFSRE0_EL1, xzr
> +alternative_else_nop_endif

This needs a 'dsb ish' prior to the msr as an indirect write (async tag
check fault) to the TFSRE0_EL1 register is not ordered with a subsequent
direct write (msr) to this register.

The check_mte_async_tcf macro is fine as we execute it after taking an
exception with SCTLR_EL1.ITFSB bit set (which triggers such
synchronisation).

--
Catalin